@@ -83,14 +83,14 @@ class LiveRegUnits {
8383 bool empty () const { return Units.none (); }
8484
8585 // / Adds register units covered by physical register \p Reg.
86- void addReg (MCPhysReg Reg) {
86+ void addReg (MCRegister Reg) {
8787 for (MCRegUnit Unit : TRI->regunits (Reg))
8888 Units.set (Unit);
8989 }
9090
9191 // / Adds register units covered by physical register \p Reg that are
9292 // / part of the lanemask \p Mask.
93- void addRegMasked (MCPhysReg Reg, LaneBitmask Mask) {
93+ void addRegMasked (MCRegister Reg, LaneBitmask Mask) {
9494 for (MCRegUnitMaskIterator Unit (Reg, TRI); Unit.isValid (); ++Unit) {
9595 LaneBitmask UnitMask = (*Unit).second ;
9696 if ((UnitMask & Mask).any ())
@@ -99,7 +99,7 @@ class LiveRegUnits {
9999 }
100100
101101 // / Removes all register units covered by physical register \p Reg.
102- void removeReg (MCPhysReg Reg) {
102+ void removeReg (MCRegister Reg) {
103103 for (MCRegUnit Unit : TRI->regunits (Reg))
104104 Units.reset (Unit);
105105 }
@@ -113,7 +113,7 @@ class LiveRegUnits {
113113 void addRegsInMask (const uint32_t *RegMask);
114114
115115 // / Returns true if no part of physical register \p Reg is live.
116- bool available (MCPhysReg Reg) const {
116+ bool available (MCRegister Reg) const {
117117 for (MCRegUnit Unit : TRI->regunits (Reg)) {
118118 if (Units.test (Unit))
119119 return false ;
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