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[AArch64][SME] Add support for zeroing ZT0 to CommitZASavePseudo (llvm#166360)
This will be used to support ZT0 in the MachineSMEABIPass.
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4 files changed

+79
-7
lines changed

4 files changed

+79
-7
lines changed

‎llvm/lib/Target/AArch64/AArch64ExpandPseudoInsts.cpp‎

Lines changed: 9 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1063,6 +1063,7 @@ AArch64ExpandPseudo::expandCommitZASave(MachineBasicBlock &MBB,
10631063
MachineBasicBlock::iterator MBBI) {
10641064
MachineInstr &MI = *MBBI;
10651065
DebugLoc DL = MI.getDebugLoc();
1066+
[[maybe_unused]] auto *RI = MBB.getParent()->getSubtarget().getRegisterInfo();
10661067

10671068
// Compare TPIDR2_EL0 against 0. Commit ZA if TPIDR2_EL0 is non-zero.
10681069
MachineInstrBuilder Branch =
@@ -1073,21 +1074,25 @@ AArch64ExpandPseudo::expandCommitZASave(MachineBasicBlock &MBB,
10731074
MachineInstrBuilder MIB =
10741075
BuildMI(CondBB, CondBB.back(), DL, TII->get(AArch64::BL));
10751076
// Copy operands (mainly the regmask) from the pseudo.
1076-
for (unsigned I = 2; I < MI.getNumOperands(); ++I)
1077+
for (unsigned I = 3; I < MI.getNumOperands(); ++I)
10771078
MIB.add(MI.getOperand(I));
10781079
// Clear TPIDR2_EL0.
10791080
BuildMI(CondBB, CondBB.back(), DL, TII->get(AArch64::MSR))
10801081
.addImm(AArch64SysReg::TPIDR2_EL0)
10811082
.addReg(AArch64::XZR);
10821083
bool ZeroZA = MI.getOperand(1).getImm() != 0;
1084+
bool ZeroZT0 = MI.getOperand(2).getImm() != 0;
10831085
if (ZeroZA) {
1084-
[[maybe_unused]] auto *TRI =
1085-
MBB.getParent()->getSubtarget().getRegisterInfo();
1086-
assert(MI.definesRegister(AArch64::ZAB0, TRI) && "should define ZA!");
1086+
assert(MI.definesRegister(AArch64::ZAB0, RI) && "should define ZA!");
10871087
BuildMI(CondBB, CondBB.back(), DL, TII->get(AArch64::ZERO_M))
10881088
.addImm(ZERO_ALL_ZA_MASK)
10891089
.addDef(AArch64::ZAB0, RegState::ImplicitDefine);
10901090
}
1091+
if (ZeroZT0) {
1092+
assert(MI.definesRegister(AArch64::ZT0, RI) && "should define ZT0!");
1093+
BuildMI(CondBB, CondBB.back(), DL, TII->get(AArch64::ZERO_T))
1094+
.addDef(AArch64::ZT0);
1095+
}
10911096

10921097
MI.eraseFromParent();
10931098
return &EndBB;

‎llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -108,7 +108,8 @@ def SMEStateAllocPseudo : Pseudo<(outs), (ins), []>, Sched<[]>;
108108

109109
def CommitZASavePseudo
110110
: Pseudo<(outs),
111-
(ins GPR64:$tpidr2_el0, i1imm:$zero_za, i64imm:$commit_routine, variable_ops), []>,
111+
(ins GPR64:$tpidr2_el0, i1imm:$zero_za, i1imm:$zero_zt0,
112+
i64imm:$commit_routine, variable_ops), []>,
112113
Sched<[]>;
113114

114115
def AArch64_inout_za_use

‎llvm/lib/Target/AArch64/MachineSMEABIPass.cpp‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -842,6 +842,7 @@ void MachineSMEABI::emitNewZAPrologue(MachineBasicBlock &MBB,
842842
BuildMI(MBB, MBBI, DL, TII->get(AArch64::CommitZASavePseudo))
843843
.addReg(TPIDR2EL0)
844844
.addImm(ZeroZA ? 1 : 0)
845+
.addImm(/*ZeroZT0=*/false)
845846
.addExternalSymbol(TLI->getLibcallName(RTLIB::SMEABI_TPIDR2_SAVE))
846847
.addRegMask(TRI->SMEABISupportRoutinesCallPreservedMaskFromX0());
847848
if (ZeroZA)

‎llvm/test/CodeGen/AArch64/expand-sme-pseudos.mir‎

Lines changed: 67 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -62,7 +62,7 @@ body: |
6262
; CHECK-NEXT: RET undef $lr
6363
$x8 = MRS 56965, implicit-def $nzcv
6464
65-
CommitZASavePseudo $x8, 0, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
65+
CommitZASavePseudo $x8, 0, 0, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0
6666
6767
RET_ReallyLR
6868
@@ -94,7 +94,72 @@ body: |
9494
; CHECK-NEXT: RET undef $lr
9595
$x8 = MRS 56965, implicit-def $nzcv
9696
97-
CommitZASavePseudo $x8, 1, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zab0
97+
CommitZASavePseudo $x8, 1, 0, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zab0
98+
99+
RET_ReallyLR
100+
101+
...
102+
---
103+
# X8 = TPIDR2_EL0
104+
name: commit_za_save_zero_zt0
105+
alignment: 4
106+
tracksRegLiveness: true
107+
body: |
108+
bb.0:
109+
; CHECK-LABEL: name: commit_za_save_zero_zt0
110+
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
111+
; CHECK-NEXT: {{ $}}
112+
; CHECK-NEXT: $x8 = MRS 56965, implicit-def $nzcv
113+
; CHECK-NEXT: CBNZX $x8, %bb.1
114+
; CHECK-NEXT: B %bb.2
115+
; CHECK-NEXT: {{ $}}
116+
; CHECK-NEXT: .1:
117+
; CHECK-NEXT: successors: %bb.2(0x80000000)
118+
; CHECK-NEXT: liveins: $x8
119+
; CHECK-NEXT: {{ $}}
120+
; CHECK-NEXT: BL &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $lr, implicit $sp, implicit-def $zt0
121+
; CHECK-NEXT: MSR 56965, $xzr
122+
; CHECK-NEXT: $zt0 = ZERO_T
123+
; CHECK-NEXT: B %bb.2
124+
; CHECK-NEXT: {{ $}}
125+
; CHECK-NEXT: .2:
126+
; CHECK-NEXT: RET undef $lr
127+
$x8 = MRS 56965, implicit-def $nzcv
128+
129+
CommitZASavePseudo $x8, 0, 1, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zt0
130+
131+
RET_ReallyLR
132+
133+
...
134+
---
135+
# X8 = TPIDR2_EL0
136+
name: commit_za_save_zero_everything
137+
alignment: 4
138+
tracksRegLiveness: true
139+
body: |
140+
bb.0:
141+
; CHECK-LABEL: name: commit_za_save_zero_everything
142+
; CHECK: successors: %bb.1(0x40000000), %bb.2(0x40000000)
143+
; CHECK-NEXT: {{ $}}
144+
; CHECK-NEXT: $x8 = MRS 56965, implicit-def $nzcv
145+
; CHECK-NEXT: CBNZX $x8, %bb.1
146+
; CHECK-NEXT: B %bb.2
147+
; CHECK-NEXT: {{ $}}
148+
; CHECK-NEXT: .1:
149+
; CHECK-NEXT: successors: %bb.2(0x80000000)
150+
; CHECK-NEXT: liveins: $x8
151+
; CHECK-NEXT: {{ $}}
152+
; CHECK-NEXT: BL &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $lr, implicit $sp, implicit-def $zab0, implicit-def $zt0
153+
; CHECK-NEXT: MSR 56965, $xzr
154+
; CHECK-NEXT: ZERO_M 255, implicit-def $zab0
155+
; CHECK-NEXT: $zt0 = ZERO_T
156+
; CHECK-NEXT: B %bb.2
157+
; CHECK-NEXT: {{ $}}
158+
; CHECK-NEXT: .2:
159+
; CHECK-NEXT: RET undef $lr
160+
$x8 = MRS 56965, implicit-def $nzcv
161+
162+
CommitZASavePseudo $x8, 1, 1, &__arm_tpidr2_save, csr_aarch64_sme_abi_support_routines_preservemost_from_x0, implicit-def $zab0, implicit-def $zt0
98163
99164
RET_ReallyLR
100165

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