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| 1 | +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5 |
| 2 | +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s |
| 3 | + |
| 4 | +define void @test(ptr %a, i32 %0, i32 %1, i1 %cmp1) { |
| 5 | +; CHECK-LABEL: define void @test( |
| 6 | +; CHECK-SAME: ptr [[A:%.*]], i32 [[TMP0:%.*]], i32 [[TMP1:%.*]], i1 [[CMP1:%.*]]) { |
| 7 | +; CHECK-NEXT: [[ENTRY:.*:]] |
| 8 | +; CHECK-NEXT: [[TMP2:%.*]] = load i32, ptr [[A]], align 4 |
| 9 | +; CHECK-NEXT: [[TOBOOL10_NOT:%.*]] = icmp eq i32 [[TMP0]], 0 |
| 10 | +; CHECK-NEXT: [[CMP4_3:%.*]] = icmp ne i32 [[TMP1]], 0 |
| 11 | +; CHECK-NEXT: [[TMP3:%.*]] = and i1 [[CMP4_3]], [[TOBOOL10_NOT]] |
| 12 | +; CHECK-NEXT: [[CMP2_2:%.*]] = xor i1 [[TOBOOL10_NOT]], true |
| 13 | +; CHECK-NEXT: [[CONV3_2:%.*]] = zext i1 [[CMP2_2]] to i32 |
| 14 | +; CHECK-NEXT: [[CMP4_2:%.*]] = icmp ne i32 [[TMP2]], [[CONV3_2]] |
| 15 | +; CHECK-NEXT: [[CMP2_1:%.*]] = xor i1 [[CMP1]], true |
| 16 | +; CHECK-NEXT: [[CONV3_1:%.*]] = zext i1 [[CMP2_1]] to i32 |
| 17 | +; CHECK-NEXT: [[CMP4_1:%.*]] = icmp ne i32 [[TMP2]], [[CONV3_1]] |
| 18 | +; CHECK-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i1 [[CMP4_2]], i1 false |
| 19 | +; CHECK-NEXT: [[TMP5:%.*]] = select i1 [[TMP4]], i1 [[CMP4_1]], i1 false |
| 20 | +; CHECK-NEXT: [[AND_3:%.*]] = zext i1 [[TMP5]] to i32 |
| 21 | +; CHECK-NEXT: store i32 [[AND_3]], ptr [[A]], align 4 |
| 22 | +; CHECK-NEXT: ret void |
| 23 | +; |
| 24 | +entry: |
| 25 | + %2 = load i32, ptr %a, align 4 |
| 26 | + %tobool10.not = icmp eq i32 %0, 0 |
| 27 | + %cmp4.3 = icmp ne i32 %1, 0 |
| 28 | + %3 = and i1 %cmp4.3, %tobool10.not |
| 29 | + %cmp2.2 = xor i1 %tobool10.not, true |
| 30 | + %conv3.2 = zext i1 %cmp2.2 to i32 |
| 31 | + %cmp4.2 = icmp ne i32 %2, %conv3.2 |
| 32 | + %cmp2.1 = xor i1 %cmp1, true |
| 33 | + %conv3.1 = zext i1 %cmp2.1 to i32 |
| 34 | + %cmp4.1 = icmp ne i32 %2, %conv3.1 |
| 35 | + %4 = select i1 %3, i1 %cmp4.2, i1 false |
| 36 | + %5 = select i1 %4, i1 %cmp4.1, i1 false |
| 37 | + %and.3 = zext i1 %5 to i32 |
| 38 | + store i32 %and.3, ptr %a, align 4 |
| 39 | + ret void |
| 40 | +} |
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