fix(vmm): Changes T2A to set RstrFpErrPtrs bit

[ Upstream commit 50b9fce ]

According to AMD APM, the RstrFpErrPtrs bit (CPUID.0x80000008:EBX[2])
indicates that FXSAVE, XSAVE, FXSAVEOPT, XSAVEC, XSAVES always save
error pointers and FXRSTOR, XRSTOR, XRSTORS always restore error
pointers.

Historically, the error pointers have been saved on Intel CPUs but were
not on old AMD CPUs (called "FXSAVE leak"). To handle this difference,
the linux kernel enables a workaround. See the following commit for more
details.
torvalds/linux@18bd057b1408

Given this sitaution, AMD decided to make their CPUs behave same as
Intel CPUs and also added the CPUID bit to let softwares know this
behavior.
torvalds/linux@f2dbad36c55e

In terms of KVM, KVM forgot to expose bit until kernel 5.4 via
KVM_GET_SUPPORTED_CPUID and has passed through from host since the
following commit.
torvalds/linux@504ce1954fba

As this bit is set on m6a.metal and the T2A template aims to provide
feature parity with guests on Intel Cascade Lake and Ice Lake with the
T2CL template, it would be better to set this bit in the T2A template.
Given the fact that firecracker supports not only kernel 5.10 but also
4.14 (where the pass-through by KVM has not been available), the T2A
template should set the bit to 1 rather than passing through.

Signed-off-by: Takahiro Itazuri <[email protected]>

Author: zulinx86

CHANGELOG.md

@@ -6,6 +6,8 @@
 
 - Fixed the T2A CPU template not to unset the MMX bit (CPUID.80000001h:EDX[23])
   and the FXSR bit (CPUID.80000001h:EDX[24]).
+- Fixed the T2A CPU template to set the RstrFpErrPtrs bit
+  (CPUID.80000008h:EBX[2]).
 
 ## [1.4.0]
 

resources/tests/static_cpu_templates/t2a.json

@@ -82,7 +82,7 @@
       "modifiers": [
         {
           "register": "ebx",
-          "bitmap": "0bxxxxxxxxxxx111xxxxxxxx0xxxxxx0x0"
+          "bitmap": "0bxxxxxxxxxxx111xxxxxxxx0xxxxxx1x0"
         }
       ]
     }

src/vmm/src/cpu_config/x86_64/static_cpu_templates/t2a.rs

@@ -122,7 +122,7 @@ pub fn t2a() -> CustomCpuTemplate {
                     register: CpuidRegister::Ebx,
                     bitmap: RegisterValueFilter {
                         filter: 0b00000000000111000000001000000101,
-                        value: 0b00000000000111000000000000000000,
+                        value: 0b00000000000111000000000000000100,
                     },
                 }],
             },

tests/integration_tests/functional/test_feat_parity.py

@@ -133,7 +133,6 @@ def test_feat_parity_cpuid_inst_set(vm):
         ),
         (0x80000008, 0x0, "ebx",
             (1 << 0) | # CLZERO
-            (1 << 2) | # RstrFpErrPtrs
             (1 << 4) | # RDPRU
             (1 << 8) | # MCOMMIT
             (1 << 9) | # WBNOINVD