refactor(cpu-template-helper): Exclude meaningless MSRs for x86_64

The previous commit made `dump_cpu_config()` not exclude MSRs that can
be dumped but are not meaningful in CPU template lifecycle. Instead,
excludes those MSRs on the CPU template helper tool's side.

Signed-off-by: Takahiro Itazuri <[email protected]>

Author: zulinx86

src/cpu-template-helper/src/template/dump/x86_64.rs

@@ -3,11 +3,15 @@
 
 use std::collections::HashMap;
 
+use vmm::arch::x86_64::msr::MsrRange;
+use vmm::arch_gen::x86::msr_index::*;
 use vmm::cpu_config::templates::{CpuConfiguration, CustomCpuTemplate, RegisterValueFilter};
-use vmm::cpu_config::x86_64::cpuid::Cpuid;
+use vmm::cpu_config::x86_64::cpuid::common::get_vendor_id_from_host;
+use vmm::cpu_config::x86_64::cpuid::{Cpuid, VENDOR_ID_AMD};
 use vmm::cpu_config::x86_64::custom_cpu_template::{
     CpuidLeafModifier, CpuidRegister, CpuidRegisterModifier, RegisterModifier,
 };
+use vmm::MSR_RANGE;
 
 use crate::utils::x86_64::{cpuid_leaf_modifier, cpuid_reg_modifier, msr_modifier};
 
@@ -45,10 +49,72 @@ fn msrs_to_modifier(msrs: &HashMap<u32, u64>) -> Vec<RegisterModifier> {
         .iter()
         .map(|(index, value)| msr_modifier!(*index, *value))
         .collect();
+
+    msrs.retain(|modifier| !should_exclude_msr(modifier.addr));
+    if &get_vendor_id_from_host().unwrap() == VENDOR_ID_AMD {
+        msrs.retain(|modifier| !should_exclude_msr_amd(modifier.addr));
+    }
+
     msrs.sort_by_key(|modifier| modifier.addr);
     msrs
 }
 
+// List of MSR indices excluded from the CPU configuration dump.
+//
+// MSRs that vary depending on the elapsed time (e.g., time stamp counter) are not useful, because
+// CPU configuration dump is used to check diff between CPU models and detect changes caused by
+// Firecracker/KVM/BIOS changes.
+//
+// Fireracker diables some features (e.g., PMU) and doesn't support some features (e.g., Hyper-V),
+// MSRs related to such features are not useful as CPU configuration dump. Excluding such MSRs
+// reduces maintenance cost when KVM makes change their default values.
+const MSR_EXCLUSION_LIST: [MsrRange; 9] = [
+    // - MSR_IA32_TSC (0x10): vary depending on the elapsed time.
+    MSR_RANGE!(MSR_IA32_TSC),
+    // Firecracker doesn't support MCE.
+    // - MSR_IA32_MCG_STATUS (0x17a)
+    // - MSR_IA32_MCG_EXT_CTL (0x4d0)
+    MSR_RANGE!(MSR_IA32_MCG_STATUS),
+    MSR_RANGE!(MSR_IA32_MCG_EXT_CTL),
+    // - MSR_IA32_PERF_CAPABILITIES (0x345) available if CPUID.01h:ECX[15] = 1 but disabled in the
+    //   CPUID normalization process.
+    MSR_RANGE!(MSR_IA32_PERF_CAPABILITIES),
+    // Firecracker doesn't support PEBS (Precise Event-Based Sampling) that is part of Intel's PMU.
+    // - MSR_IA32_PEBS_ENABLE (0x3F1)
+    // - MSR_PEBS_DATA_CFG (0x3F2)
+    // - MSR_IA32_DS_AREA (0x600)
+    MSR_RANGE!(MSR_IA32_PEBS_ENABLE, 2),
+    MSR_RANGE!(MSR_IA32_DS_AREA),
+    // Firecracker doesn't support AMD PMU.
+    // - MSR_K7_EVNTSELn (0xC0010000..=0xC0010003)
+    // - MSR_K7_PERFCTRn (0xC0010004..=0xC0010007)
+    // - MSR_F15H_PERF_CTLn & MSR_F15H_PERF_CTRn (0xC0010200..=0xC001020B)
+    MSR_RANGE!(MSR_K7_EVNTSEL0, 4),
+    MSR_RANGE!(MSR_K7_PERFCTR0, 4),
+    MSR_RANGE!(MSR_F15H_PERF_CTL0, 12),
+];
+
+fn should_exclude_msr(index: u32) -> bool {
+    MSR_EXCLUSION_LIST.iter().any(|range| range.contains(index))
+}
+
+// List of MSR indices excluded from the CPU configuration dump on AMD
+const MSR_EXCLUSION_LIST_AMD: [MsrRange; 1] = [
+    // MSR_IA32_ARCH_CAPABILITIES has been emulated by KVM since kernel 5.7.
+    // https://github.com/torvalds/linux/commit/93c380e7b528882396ca463971012222bad7d82e
+    // https://lore.kernel.org/all/[email protected]/
+    // As this MSR is not available on AMD processors, Firecracker disables it explicitly by
+    // setting 0 to CPUID.(EAX=07H,ECX=0):EDX[bit 29], and this MSR should be removed from the
+    // dump on AMD.
+    MSR_RANGE!(MSR_IA32_ARCH_CAPABILITIES),
+];
+
+fn should_exclude_msr_amd(index: u32) -> bool {
+    MSR_EXCLUSION_LIST_AMD
+        .iter()
+        .any(|range| range.contains(index))
+}
+
 #[cfg(test)]
 mod tests {
     use std::collections::BTreeMap;
@@ -122,25 +188,44 @@ mod tests {
     }
 
     fn build_sample_msrs() -> HashMap<u32, u64> {
-        HashMap::from([
+        let mut map = HashMap::from([
+            // should be sorted in the result.
             (0x1, 0xffff_ffff_ffff_ffff),
             (0x5, 0xffff_ffff_0000_0000),
             (0x3, 0x0000_0000_ffff_ffff),
             (0x2, 0x0000_0000_0000_0000),
-        ])
+        ]);
+        // should be excluded from the result.
+        MSR_EXCLUSION_LIST
+            .iter()
+            .chain(MSR_EXCLUSION_LIST_AMD.iter())
+            .for_each(|range| {
+                (range.base..(range.base + range.nmsrs)).for_each(|id| {
+                    map.insert(id, 0);
+                })
+            });
+        map
     }
 
     fn build_expected_msr_modifiers() -> Vec<RegisterModifier> {
-        vec![
+        let mut v = vec![
             msr_modifier!(0x1, 0xffff_ffff_ffff_ffff),
             msr_modifier!(0x2, 0x0000_0000_0000_0000),
             msr_modifier!(0x3, 0x0000_0000_ffff_ffff),
             msr_modifier!(0x5, 0xffff_ffff_0000_0000),
-        ]
+        ];
+        if &get_vendor_id_from_host().unwrap() != VENDOR_ID_AMD {
+            MSR_EXCLUSION_LIST_AMD.iter().for_each(|range| {
+                (range.base..(range.base + range.nmsrs)).for_each(|id| {
+                    v.push(msr_modifier!(id, 0));
+                })
+            });
+        }
+        v
     }
 
     #[test]
-    fn test_cpuid_to_modifier() {
+    fn test_config_to_template() {
         let cpu_config = CpuConfiguration {
             cpuid: build_sample_cpuid(),
             msrs: build_sample_msrs(),

src/vmm/src/arch/x86_64/msr.rs

@@ -29,16 +29,16 @@ pub enum MsrError {
 
 /// MSR range
 #[derive(Debug)]
-struct MsrRange {
+pub struct MsrRange {
     /// Base MSR address
-    base: u32,
+    pub base: u32,
     /// Number of MSRs
-    nmsrs: u32,
+    pub nmsrs: u32,
 }
 
 impl MsrRange {
     /// Returns whether `msr` is contained in this MSR range.
-    fn contains(&self, msr: u32) -> bool {
+    pub fn contains(&self, msr: u32) -> bool {
         self.base <= msr && msr < self.base + self.nmsrs
     }
 }
@@ -127,7 +127,8 @@ bitflags! {
     }
 }
 
-// Macro for generating a MsrRange.
+/// Macro for generating a MsrRange.
+#[macro_export]
 macro_rules! MSR_RANGE {
     ($base:expr, $nmsrs:expr) => {
         MsrRange {