fix: Cache level

Corrects the `cache_level` variables under
`update_deterministic_cache_entry` and
`update_extended_cache_topology_entry` to get the cache level, where
previously they where mistakenly getting the cache type.

Signed-off-by: Jonathan Woollett-Light <[email protected]>

Author: Jonathan Woollett-Light

resources/tests/cpu_template_helper/cpu_config_AMD_MILAN_4.14host.json

@@ -1157,7 +1157,7 @@
       "modifiers": [
         {
           "register": "eax",
-          "bitmap": "0b00000000000000000100000101000011"
+          "bitmap": "0b00000000000000000000000101000011"
         },
         {
           "register": "ebx",

resources/tests/cpu_template_helper/cpu_config_AMD_MILAN_5.10host.json

@@ -1249,7 +1249,7 @@
       "modifiers": [
         {
           "register": "eax",
-          "bitmap": "0b00000000000000000100000101000011"
+          "bitmap": "0b00000000000000000000000101000011"
         },
         {
           "register": "ebx",

resources/tests/cpu_template_helper/cpu_config_INTEL_CASCADELAKE_4.14host.json

@@ -145,7 +145,7 @@
       "modifiers": [
         {
           "register": "eax",
-          "bitmap": "0b00000100000000000100000101000011"
+          "bitmap": "0b00000100000000000000000101000011"
         },
         {
           "register": "ebx",

resources/tests/cpu_template_helper/cpu_config_INTEL_CASCADELAKE_5.10host.json

@@ -145,7 +145,7 @@
       "modifiers": [
         {
           "register": "eax",
-          "bitmap": "0b00000100000000000100000101000011"
+          "bitmap": "0b00000100000000000000000101000011"
         },
         {
           "register": "ebx",

resources/tests/cpu_template_helper/cpu_config_INTEL_ICELAKE_4.14host.json

@@ -145,7 +145,7 @@
       "modifiers": [
         {
           "register": "eax",
-          "bitmap": "0b00000100000000000100000101000011"
+          "bitmap": "0b00000100000000000000000101000011"
         },
         {
           "register": "ebx",

resources/tests/cpu_template_helper/cpu_config_INTEL_ICELAKE_5.10host.json

@@ -145,7 +145,7 @@
       "modifiers": [
         {
           "register": "eax",
-          "bitmap": "0b00000100000000000100000101000011"
+          "bitmap": "0b00000100000000000000000101000011"
         },
         {
           "register": "ebx",

resources/tests/cpu_template_helper/cpu_config_INTEL_SKYLAKE_4.14host.json

@@ -145,7 +145,7 @@
       "modifiers": [
         {
           "register": "eax",
-          "bitmap": "0b00000100000000000100000101000011"
+          "bitmap": "0b00000100000000000000000101000011"
         },
         {
           "register": "ebx",

resources/tests/cpu_template_helper/cpu_config_INTEL_SKYLAKE_5.10host.json

@@ -145,7 +145,7 @@
       "modifiers": [
         {
           "register": "eax",
-          "bitmap": "0b00000100000000000100000101000011"
+          "bitmap": "0b00000100000000000000000101000011"
         },
         {
           "register": "ebx",

src/vmm/src/guest_config/x86_64/cpuid/amd/normalize.rs

@@ -2,7 +2,9 @@
 // SPDX-License-Identifier: Apache-2.0
 
 use crate::guest_config::x86_64::cpuid::common::{get_vendor_id_from_host, GetCpuidError};
-use crate::guest_config::x86_64::cpuid::normalize::{set_bit, set_range, CheckedAssignError};
+use crate::guest_config::x86_64::cpuid::normalize::{
+    get_range, set_bit, set_range, CheckedAssignError,
+};
 use crate::guest_config::x86_64::cpuid::{
     cpuid, cpuid_count, CpuidEntry, CpuidKey, CpuidRegisters, CpuidTrait, KvmCpuidFlags,
     MissingBrandStringLeaves, BRAND_STRING_LENGTH, VENDOR_ID_AMD,
@@ -292,18 +294,19 @@ impl super::AmdCpuid {
     ) -> Result<(), ExtendedCacheTopologyError> {
         for i in 0.. {
             if let Some(subleaf) = self.get_mut(&CpuidKey::subleaf(0x8000001d, i)) {
-                // Cache type. Identifies the type of cache.
+                // Cache level. Identifies the level of this cache. Note that the enumeration value
+                // is not necessarily equal to the cache level.
                 // ```text
                 // Bits Description
-                // 00h Null; no more caches.
-                // 01h Data cache
-                // 02h Instruction cache
-                // 03h Unified cache
-                // 1Fh-04h Reserved.
+                // 000b Reserved.
+                // 001b Level 1
+                // 010b Level 2
+                // 011b Level 3
+                // 111b-100b Reserved.
                 // ```
                 //
-                // cache_type: 0..4,
-                let cache_level = 15 & subleaf.result.eax; // 15 == (2^4)-1
+                // cache_level: 5..8
+                let cache_level = get_range(subleaf.result.eax, 5..8);
 
                 // Specifies the number of logical processors sharing the cache enumerated by N,
                 // the value passed to the instruction in ECX. The number of logical processors

src/vmm/src/guest_config/x86_64/cpuid/intel/normalize.rs

@@ -1,7 +1,9 @@
 // Copyright 2023 Amazon.com, Inc. or its affiliates. All Rights Reserved.
 // SPDX-License-Identifier: Apache-2.0
 
-use crate::guest_config::x86_64::cpuid::normalize::{set_bit, set_range, CheckedAssignError};
+use crate::guest_config::x86_64::cpuid::normalize::{
+    get_range, set_bit, set_range, CheckedAssignError,
+};
 use crate::guest_config::x86_64::cpuid::{
     host_brand_string, CpuidKey, CpuidRegisters, CpuidTrait, MissingBrandStringLeaves,
     BRAND_STRING_LENGTH,
@@ -108,15 +110,10 @@ impl super::IntelCpuid {
                     break;
                 }
 
-                // Cache Type Field.
-                // - 0 = Null - No more caches.
-                // - 1 = Data Cache.
-                // - 2 = Instruction Cache.
-                // - 3 = Unified Cache.
-                // - 4-31 = Reserved.
+                // Cache Level (Starts at 1)
                 //
-                // cache_type_field: 0..5,
-                let cache_level = subleaf.result.eax & 15;
+                // cache_level: 5..8
+                let cache_level = get_range(subleaf.result.eax, 5..8);
 
                 // Maximum number of addressable IDs for logical processors sharing this cache.
                 // - Add one to the return value to get the result.