chore: fix hex formatting in msr baselines

ShadowCurse · ShadowCurse · commit 5771bb8a452f · 2025-06-04T11:08:50.000+01:00
Bash script was formatting 0 as 0, while C version formats it
as 0x0. Update to 0x0.

Signed-off-by: Egor Lazarchuk &lt;yegorlz@amazon.co.uk&gt;
diff --git a/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_5.10guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x7e1358a6
 0x11,0x24b8008
diff --git a/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_6.1guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_5.10_INTEL_SAPPHIRE_RAPIDS_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x6f36e74e
 0x11,0x25cb008
diff --git a/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xbae96682
 0x11,0x24a1008
diff --git a/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv b/tests/data/msr/msr_list_SPR_TO_T2_6.1_INTEL_SAPPHIRE_RAPIDS_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x7b423550
 0x11,0x25cb008
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xfd7a7f6d
 0x11,0x2501008
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xfd7a7f6d
 0x11,0x2501008
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xd2adc3c4
 0x11,0x2a00000
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xd2adc3c4
 0x11,0x2a00000
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xbe7f66e8
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xbe7f66e8
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xf8c468e6
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xf8c468e6
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x114970c7a
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x114970c7a
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x119817846
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x119817846
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xc1aa1fac
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xc1aa1fac
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xf68480f8
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xf68480f8
 0x11,0x2502008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xff34f950
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0xff34f950
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_5.10guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_5.10guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x1000556b4
 0x11,0x2748008
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_6.1guest.csv
@@ -1,5 +1,5 @@
 MSR_ADDR,VALUE
-0,0x0
+0x0,0x0
 0x1,0x0
 0x10,0x1000556b4
 0x11,0x2748008
