pci: document potential contention on PCI bus lock

We have a single lock for all devices on the PCI bus that serializes
reads and writes on the devices' PCI configuration space and BARs.

This should not be a problem at the moment. It should be out of any hot
path and only up until we are setting up devices. However, add a comment
that mentions the existence of the contention so that we keep it in mind
for the futuer (and maybe perform some profiling).

Signed-off-by: Babis Chalios <[email protected]>

Author: bchalios

src/pci/src/bus.rs

@@ -161,6 +161,9 @@ impl PciConfigIo {
             return 0xffff_ffff;
         }
 
+        // NOTE: Potential contention among vCPU threads on this lock. This should not
+        // be a problem currently, since we mainly access this when we are setting up devices.
+        // We might want to do some profiling to ensure this does not become a bottleneck.
         self.pci_bus
             .as_ref()
             .lock()
@@ -195,6 +198,9 @@ impl PciConfigIo {
             return None;
         }
 
+        // NOTE: Potential contention among vCPU threads on this lock. This should not
+        // be a problem currently, since we mainly access this when we are setting up devices.
+        // We might want to do some profiling to ensure this does not become a bottleneck.
         let pci_bus = self.pci_bus.as_ref().lock().unwrap();
         if let Some(d) = pci_bus.devices.get(&(device as u32)) {
             let mut device = d.lock().unwrap();