fix(vmm): Disable SVM on T2A template

Althought T2A and T2CL templates together aim to provide instruction set
feature parity, T2CL disables nested virtualization (VMX) but T2A does
not disable it (SVM). This commit disables SVM on T2A template.

Signed-off-by: Takahiro Itazuri <[email protected]>

Author: zulinx86

CHANGELOG.md

@@ -38,6 +38,7 @@
   IA32_ARCH_CAPABILITIES MSR from the host in accordance with an Intel microcode
   update.
 - Fixed passing through cache information from host in CPUID leaf 0x80000005.
+- Fixed the T2A CPU template to disable SVM (nested virtualization).
 
 ## [1.3.0]
 

resources/tests/static_cpu_templates/t2a.json

@@ -67,7 +67,7 @@
       "modifiers": [
         {
           "register": "ecx",
-          "bitmap": "0bxx0xxxxxxxxxxxxxxxxxxxx000xxxxxx"
+          "bitmap": "0bxx0xxxxxxxxxxxxxxxxxxxx000xxx0xx"
         },
         {
           "register": "edx",

src/vmm/src/cpu_config/x86_64/static_cpu_templates/t2a.rs

@@ -194,14 +194,15 @@ pub fn t2a() -> CustomCpuTemplate {
                 flags: KvmCpuidFlags(0),
                 modifiers: vec![
                     // ECX:
+                    // - Bit 02: SVM (AMD APM) / Reserved (Intel SDM)
                     // - Bit 06: SSE4A (AMD APM) / Reserved (Intel SDM)
                     // - Bit 07: MisAlignSse (AMD APM) / Reserved (Intel SDM)
                     // - Bit 08: 3DNowPrefetch (AMD APM) / PREFETCHW (Intel SDM)
                     // - Bit 29: MONITORX (AMD APM) / MONITORX and MWAITX (Intel SDM)
                     CpuidRegisterModifier {
                         register: CpuidRegister::Ecx,
                         bitmap: RegisterValueFilter {
-                            filter: 0b0010_0000_0000_0000_0000_0001_1100_0000,
+                            filter: 0b0010_0000_0000_0000_0000_0001_1100_0100,
                             value: 0b0000_0000_0000_0000_0000_0000_0000_0000,
                         },
                     },