chore(bindgen): upgrade to linux 6.12 headers and use single kernel tree

We were using bindgen from 3 different sources:
 - installed headers in the system
 - linux-5.10.y branch from amazonlinux repo
 - linux-next branch from torvalds repo

This is overcomplicated and unnecessary as Linux doesn't break the UAPI.

This patch updates it to use a single stable branch (6.12), from which
the user headers are generated using `make headers_install` and
regenerates all the headers, fixing some minor incompatibilities in the
syntax.

While I was at it I also improved the generation for C enums to use
constified-enum-module style which is less verbose.

I had to fix an issue with the io_uring auto-generated structs not
implementing Copy due to FAM introduced in the latest kernels. I have
put a bindgen-patch to drop the FAM and derive Copy and Clone where
required to implement ByteValued. If we ever need to use those fields,
we'll need to find a different solution.

Signed-off-by: Riccardo Mancini <[email protected]>

Author: Manciukic

src/firecracker/src/generated/prctl.rs

@@ -12,7 +12,8 @@
     clippy::undocumented_unsafe_blocks,
     missing_debug_implementations,
     clippy::tests_outside_test_module,
-    unsafe_op_in_unsafe_fn
+    unsafe_op_in_unsafe_fn,
+    clippy::redundant_static_lifetimes
 )]
 
 pub const PR_SET_PDEATHSIG: u32 = 1;
@@ -179,3 +180,20 @@ pub const PR_RISCV_V_VSTATE_CTRL_INHERIT: u32 = 16;
 pub const PR_RISCV_V_VSTATE_CTRL_CUR_MASK: u32 = 3;
 pub const PR_RISCV_V_VSTATE_CTRL_NEXT_MASK: u32 = 12;
 pub const PR_RISCV_V_VSTATE_CTRL_MASK: u32 = 31;
+pub const PR_RISCV_SET_ICACHE_FLUSH_CTX: u32 = 71;
+pub const PR_RISCV_CTX_SW_FENCEI_ON: u32 = 0;
+pub const PR_RISCV_CTX_SW_FENCEI_OFF: u32 = 1;
+pub const PR_RISCV_SCOPE_PER_PROCESS: u32 = 0;
+pub const PR_RISCV_SCOPE_PER_THREAD: u32 = 1;
+pub const PR_PPC_GET_DEXCR: u32 = 72;
+pub const PR_PPC_SET_DEXCR: u32 = 73;
+pub const PR_PPC_DEXCR_SBHE: u32 = 0;
+pub const PR_PPC_DEXCR_IBRTPD: u32 = 1;
+pub const PR_PPC_DEXCR_SRAPD: u32 = 2;
+pub const PR_PPC_DEXCR_NPHIE: u32 = 3;
+pub const PR_PPC_DEXCR_CTRL_EDITABLE: u32 = 1;
+pub const PR_PPC_DEXCR_CTRL_SET: u32 = 2;
+pub const PR_PPC_DEXCR_CTRL_CLEAR: u32 = 4;
+pub const PR_PPC_DEXCR_CTRL_SET_ONEXEC: u32 = 8;
+pub const PR_PPC_DEXCR_CTRL_CLEAR_ONEXEC: u32 = 16;
+pub const PR_PPC_DEXCR_CTRL_MASK: u32 = 31;

src/vmm/src/arch/x86_64/generated/arch_prctl.rs

@@ -12,7 +12,8 @@
     clippy::undocumented_unsafe_blocks,
     missing_debug_implementations,
     clippy::tests_outside_test_module,
-    unsafe_op_in_unsafe_fn
+    unsafe_op_in_unsafe_fn,
+    clippy::redundant_static_lifetimes
 )]
 
 pub const ARCH_SET_GS: u32 = 4097;

src/vmm/src/arch/x86_64/generated/hyperv.rs

@@ -12,7 +12,8 @@
     clippy::undocumented_unsafe_blocks,
     missing_debug_implementations,
     clippy::tests_outside_test_module,
-    unsafe_op_in_unsafe_fn
+    unsafe_op_in_unsafe_fn,
+    clippy::redundant_static_lifetimes
 )]
 
 pub const HV_X64_MSR_SYNDBG_CONTROL: u32 = 0x400000f1;

src/vmm/src/arch/x86_64/generated/hyperv_tlfs.rs

@@ -12,7 +12,8 @@
     clippy::undocumented_unsafe_blocks,
     missing_debug_implementations,
     clippy::tests_outside_test_module,
-    unsafe_op_in_unsafe_fn
+    unsafe_op_in_unsafe_fn,
+    clippy::redundant_static_lifetimes
 )]
 
 pub const HV_X64_MSR_GUEST_OS_ID: u32 = 0x40000000;
@@ -49,6 +50,12 @@ pub const HV_X64_MSR_SINT12: u32 = 0x4000009c;
 pub const HV_X64_MSR_SINT13: u32 = 0x4000009d;
 pub const HV_X64_MSR_SINT14: u32 = 0x4000009e;
 pub const HV_X64_MSR_SINT15: u32 = 0x4000009f;
+pub const HV_X64_MSR_NESTED_SCONTROL: u32 = 0x40001080;
+pub const HV_X64_MSR_NESTED_SVERSION: u32 = 0x40001081;
+pub const HV_X64_MSR_NESTED_SIEFP: u32 = 0x40001082;
+pub const HV_X64_MSR_NESTED_SIMP: u32 = 0x40001083;
+pub const HV_X64_MSR_NESTED_EOM: u32 = 0x40001084;
+pub const HV_X64_MSR_NESTED_SINT0: u32 = 0x40001090;
 pub const HV_X64_MSR_STIMER0_CONFIG: u32 = 0x400000b0;
 pub const HV_X64_MSR_STIMER0_COUNT: u32 = 0x400000b1;
 pub const HV_X64_MSR_STIMER1_CONFIG: u32 = 0x400000b2;

src/vmm/src/arch/x86_64/generated/mpspec.rs

@@ -12,7 +12,8 @@
     clippy::undocumented_unsafe_blocks,
     missing_debug_implementations,
     clippy::tests_outside_test_module,
-    unsafe_op_in_unsafe_fn
+    unsafe_op_in_unsafe_fn,
+    clippy::redundant_static_lifetimes
 )]
 
 pub const MPC_SIGNATURE: &[u8; 5] = b"PCMP\0";
@@ -205,11 +206,13 @@ const _: () = {
     ["Offset of field: mpc_intsrc::dstapic"][::std::mem::offset_of!(mpc_intsrc, dstapic) - 6usize];
     ["Offset of field: mpc_intsrc::dstirq"][::std::mem::offset_of!(mpc_intsrc, dstirq) - 7usize];
 };
-pub const mp_irq_source_types_mp_INT: mp_irq_source_types = 0;
-pub const mp_irq_source_types_mp_NMI: mp_irq_source_types = 1;
-pub const mp_irq_source_types_mp_SMI: mp_irq_source_types = 2;
-pub const mp_irq_source_types_mp_ExtINT: mp_irq_source_types = 3;
-pub type mp_irq_source_types = ::std::os::raw::c_uint;
+pub mod mp_irq_source_types {
+    pub type Type = ::std::os::raw::c_uint;
+    pub const mp_INT: Type = 0;
+    pub const mp_NMI: Type = 1;
+    pub const mp_SMI: Type = 2;
+    pub const mp_ExtINT: Type = 3;
+}
 #[repr(C)]
 #[derive(Debug, Default, Copy, Clone, PartialEq)]
 pub struct mpc_lintsrc {
@@ -261,7 +264,9 @@ const _: () = {
         [::std::mem::offset_of!(mpc_oemtable, checksum) - 7usize];
     ["Offset of field: mpc_oemtable::mpc"][::std::mem::offset_of!(mpc_oemtable, mpc) - 8usize];
 };
-pub const mp_bustype_MP_BUS_ISA: mp_bustype = 1;
-pub const mp_bustype_MP_BUS_EISA: mp_bustype = 2;
-pub const mp_bustype_MP_BUS_PCI: mp_bustype = 3;
-pub type mp_bustype = ::std::os::raw::c_uint;
+pub mod mp_bustype {
+    pub type Type = ::std::os::raw::c_uint;
+    pub const MP_BUS_ISA: Type = 1;
+    pub const MP_BUS_EISA: Type = 2;
+    pub const MP_BUS_PCI: Type = 3;
+}

src/vmm/src/arch/x86_64/generated/msr_index.rs

@@ -12,7 +12,8 @@
     clippy::undocumented_unsafe_blocks,
     missing_debug_implementations,
     clippy::tests_outside_test_module,
-    unsafe_op_in_unsafe_fn
+    unsafe_op_in_unsafe_fn,
+    clippy::redundant_static_lifetimes
 )]
 
 pub const MSR_EFER: u32 = 0xc0000080;
@@ -24,6 +25,15 @@ pub const MSR_FS_BASE: u32 = 0xc0000100;
 pub const MSR_GS_BASE: u32 = 0xc0000101;
 pub const MSR_KERNEL_GS_BASE: u32 = 0xc0000102;
 pub const MSR_TSC_AUX: u32 = 0xc0000103;
+pub const MSR_IA32_FRED_RSP0: u32 = 0x1cc;
+pub const MSR_IA32_FRED_RSP1: u32 = 0x1cd;
+pub const MSR_IA32_FRED_RSP2: u32 = 0x1ce;
+pub const MSR_IA32_FRED_RSP3: u32 = 0x1cf;
+pub const MSR_IA32_FRED_STKLVLS: u32 = 0x1d0;
+pub const MSR_IA32_FRED_SSP1: u32 = 0x1d1;
+pub const MSR_IA32_FRED_SSP2: u32 = 0x1d2;
+pub const MSR_IA32_FRED_SSP3: u32 = 0x1d3;
+pub const MSR_IA32_FRED_CONFIG: u32 = 0x1d4;
 pub const MSR_TEST_CTRL: u32 = 0x33;
 pub const MSR_TEST_CTRL_SPLIT_LOCK_DETECT_BIT: u32 = 0x1d;
 pub const MSR_IA32_SPEC_CTRL: u32 = 0x48;
@@ -38,6 +48,7 @@ pub const MSR_PLATFORM_INFO_CPUID_FAULT_BIT: u32 = 0x1f;
 pub const MSR_IA32_UMWAIT_CONTROL: u32 = 0xe1;
 pub const MSR_IA32_UMWAIT_CONTROL_TIME_MASK: i32 = -4;
 pub const MSR_IA32_CORE_CAPS: u32 = 0xcf;
+pub const MSR_IA32_CORE_CAPS_INTEGRITY_CAPS_BIT: u32 = 0x2;
 pub const MSR_IA32_CORE_CAPS_SPLIT_LOCK_DETECT_BIT: u32 = 0x5;
 pub const MSR_PKG_CST_CONFIG_CONTROL: u32 = 0xe2;
 pub const MSR_MTRRcap: u32 = 0xfe;
@@ -53,16 +64,23 @@ pub const MSR_IA32_SYSENTER_EIP: u32 = 0x176;
 pub const MSR_IA32_MCG_CAP: u32 = 0x179;
 pub const MSR_IA32_MCG_STATUS: u32 = 0x17a;
 pub const MSR_IA32_MCG_CTL: u32 = 0x17b;
+pub const MSR_ERROR_CONTROL: u32 = 0x17f;
 pub const MSR_IA32_MCG_EXT_CTL: u32 = 0x4d0;
 pub const MSR_OFFCORE_RSP_0: u32 = 0x1a6;
 pub const MSR_OFFCORE_RSP_1: u32 = 0x1a7;
 pub const MSR_TURBO_RATIO_LIMIT: u32 = 0x1ad;
 pub const MSR_TURBO_RATIO_LIMIT1: u32 = 0x1ae;
 pub const MSR_TURBO_RATIO_LIMIT2: u32 = 0x1af;
+pub const MSR_SNOOP_RSP_0: u32 = 0x1328;
+pub const MSR_SNOOP_RSP_1: u32 = 0x1329;
 pub const MSR_LBR_SELECT: u32 = 0x1c8;
 pub const MSR_LBR_TOS: u32 = 0x1c9;
 pub const MSR_IA32_POWER_CTL: u32 = 0x1fc;
 pub const MSR_IA32_POWER_CTL_BIT_EE: u32 = 0x13;
+pub const MSR_INTEGRITY_CAPS: u32 = 0x2d9;
+pub const MSR_INTEGRITY_CAPS_ARRAY_BIST_BIT: u32 = 0x2;
+pub const MSR_INTEGRITY_CAPS_PERIODIC_BIST_BIT: u32 = 0x4;
+pub const MSR_INTEGRITY_CAPS_SBAF_BIT: u32 = 0x8;
 pub const MSR_LBR_NHM_FROM: u32 = 0x680;
 pub const MSR_LBR_NHM_TO: u32 = 0x6c0;
 pub const MSR_LBR_CORE_FROM: u32 = 0x40;
@@ -133,6 +151,7 @@ pub const MSR_PKGC7_IRTL: u32 = 0x60c;
 pub const MSR_PKGC8_IRTL: u32 = 0x633;
 pub const MSR_PKGC9_IRTL: u32 = 0x634;
 pub const MSR_PKGC10_IRTL: u32 = 0x635;
+pub const MSR_VR_CURRENT_CONFIG: u32 = 0x601;
 pub const MSR_RAPL_POWER_UNIT: u32 = 0x606;
 pub const MSR_PKG_POWER_LIMIT: u32 = 0x610;
 pub const MSR_PKG_ENERGY_STATUS: u32 = 0x611;
@@ -149,14 +168,16 @@ pub const MSR_PP0_PERF_STATUS: u32 = 0x63b;
 pub const MSR_PP1_POWER_LIMIT: u32 = 0x640;
 pub const MSR_PP1_ENERGY_STATUS: u32 = 0x641;
 pub const MSR_PP1_POLICY: u32 = 0x642;
-pub const MSR_AMD_PKG_ENERGY_STATUS: u32 = 0xc001029b;
 pub const MSR_AMD_RAPL_POWER_UNIT: u32 = 0xc0010299;
+pub const MSR_AMD_CORE_ENERGY_STATUS: u32 = 0xc001029a;
+pub const MSR_AMD_PKG_ENERGY_STATUS: u32 = 0xc001029b;
 pub const MSR_CONFIG_TDP_NOMINAL: u32 = 0x648;
 pub const MSR_CONFIG_TDP_LEVEL_1: u32 = 0x649;
 pub const MSR_CONFIG_TDP_LEVEL_2: u32 = 0x64a;
 pub const MSR_CONFIG_TDP_CONTROL: u32 = 0x64b;
 pub const MSR_TURBO_ACTIVATION_RATIO: u32 = 0x64c;
 pub const MSR_PLATFORM_ENERGY_STATUS: u32 = 0x64d;
+pub const MSR_SECONDARY_TURBO_RATIO_LIMIT: u32 = 0x650;
 pub const MSR_PKG_WEIGHTED_CORE_C0_RES: u32 = 0x658;
 pub const MSR_PKG_ANY_CORE_C0_RES: u32 = 0x659;
 pub const MSR_PKG_ANY_GFXE_C0_RES: u32 = 0x65a;
@@ -172,6 +193,13 @@ pub const MSR_ATOM_CORE_TURBO_VIDS: u32 = 0x66d;
 pub const MSR_CORE_PERF_LIMIT_REASONS: u32 = 0x690;
 pub const MSR_GFX_PERF_LIMIT_REASONS: u32 = 0x6b0;
 pub const MSR_RING_PERF_LIMIT_REASONS: u32 = 0x6b1;
+pub const MSR_IA32_U_CET: u32 = 0x6a0;
+pub const MSR_IA32_S_CET: u32 = 0x6a2;
+pub const MSR_IA32_PL0_SSP: u32 = 0x6a4;
+pub const MSR_IA32_PL1_SSP: u32 = 0x6a5;
+pub const MSR_IA32_PL2_SSP: u32 = 0x6a6;
+pub const MSR_IA32_PL3_SSP: u32 = 0x6a7;
+pub const MSR_IA32_INT_SSP_TAB: u32 = 0x6a8;
 pub const MSR_PPERF: u32 = 0x64e;
 pub const MSR_PERF_LIMIT_REASONS: u32 = 0x64f;
 pub const MSR_PM_ENABLE: u32 = 0x770;
@@ -193,6 +221,11 @@ pub const MSR_KNC_EVNTSEL1: u32 = 0x29;
 pub const MSR_IA32_PMC0: u32 = 0x4c1;
 pub const MSR_RELOAD_PMC0: u32 = 0x14c1;
 pub const MSR_RELOAD_FIXED_CTR0: u32 = 0x1309;
+pub const MSR_IA32_PMC_V6_GP0_CTR: u32 = 0x1900;
+pub const MSR_IA32_PMC_V6_GP0_CFG_A: u32 = 0x1901;
+pub const MSR_IA32_PMC_V6_FX0_CTR: u32 = 0x1980;
+pub const MSR_IA32_PMC_V6_STEP: u32 = 0x4;
+pub const MSR_IA32_MKTME_KEYID_PARTITIONING: u32 = 0x87;
 pub const MSR_AMD64_PATCH_LEVEL: u32 = 0x8b;
 pub const MSR_AMD64_TSC_RATIO: u32 = 0xc0000104;
 pub const MSR_AMD64_NB_CFG: u32 = 0xc001001f;
@@ -204,6 +237,7 @@ pub const MSR_AMD64_OSVW_ID_LENGTH: u32 = 0xc0010140;
 pub const MSR_AMD64_OSVW_STATUS: u32 = 0xc0010141;
 pub const MSR_AMD_PPIN_CTL: u32 = 0xc00102f0;
 pub const MSR_AMD_PPIN: u32 = 0xc00102f1;
+pub const MSR_AMD64_CPUID_FN_7: u32 = 0xc0011002;
 pub const MSR_AMD64_CPUID_FN_1: u32 = 0xc0011004;
 pub const MSR_AMD64_LS_CFG: u32 = 0xc0011020;
 pub const MSR_AMD64_DC_CFG: u32 = 0xc0011022;
@@ -231,14 +265,44 @@ pub const MSR_AMD64_IBSBRTARGET: u32 = 0xc001103b;
 pub const MSR_AMD64_ICIBSEXTDCTL: u32 = 0xc001103c;
 pub const MSR_AMD64_IBSOPDATA4: u32 = 0xc001103d;
 pub const MSR_AMD64_IBS_REG_COUNT_MAX: u32 = 0x8;
+pub const MSR_AMD64_SVM_AVIC_DOORBELL: u32 = 0xc001011b;
 pub const MSR_AMD64_VM_PAGE_FLUSH: u32 = 0xc001011e;
 pub const MSR_AMD64_SEV_ES_GHCB: u32 = 0xc0010130;
 pub const MSR_AMD64_SEV: u32 = 0xc0010131;
 pub const MSR_AMD64_SEV_ENABLED_BIT: u32 = 0x0;
 pub const MSR_AMD64_SEV_ES_ENABLED_BIT: u32 = 0x1;
+pub const MSR_AMD64_SEV_SNP_ENABLED_BIT: u32 = 0x2;
+pub const MSR_AMD64_SNP_VTOM_BIT: u32 = 0x3;
+pub const MSR_AMD64_SNP_REFLECT_VC_BIT: u32 = 0x4;
+pub const MSR_AMD64_SNP_RESTRICTED_INJ_BIT: u32 = 0x5;
+pub const MSR_AMD64_SNP_ALT_INJ_BIT: u32 = 0x6;
+pub const MSR_AMD64_SNP_DEBUG_SWAP_BIT: u32 = 0x7;
+pub const MSR_AMD64_SNP_PREVENT_HOST_IBS_BIT: u32 = 0x8;
+pub const MSR_AMD64_SNP_BTB_ISOLATION_BIT: u32 = 0x9;
+pub const MSR_AMD64_SNP_VMPL_SSS_BIT: u32 = 0xa;
+pub const MSR_AMD64_SNP_SECURE_TSC_BIT: u32 = 0xb;
+pub const MSR_AMD64_SNP_VMGEXIT_PARAM_BIT: u32 = 0xc;
+pub const MSR_AMD64_SNP_IBS_VIRT_BIT: u32 = 0xe;
+pub const MSR_AMD64_SNP_VMSA_REG_PROT_BIT: u32 = 0x10;
+pub const MSR_AMD64_SNP_SMT_PROT_BIT: u32 = 0x11;
+pub const MSR_AMD64_SNP_RESV_BIT: u32 = 0x12;
 pub const MSR_AMD64_VIRT_SPEC_CTRL: u32 = 0xc001011f;
+pub const MSR_AMD64_RMP_BASE: u32 = 0xc0010132;
+pub const MSR_AMD64_RMP_END: u32 = 0xc0010133;
+pub const MSR_SVSM_CAA: u32 = 0xc001f000;
+pub const MSR_AMD_CPPC_CAP1: u32 = 0xc00102b0;
+pub const MSR_AMD_CPPC_ENABLE: u32 = 0xc00102b1;
+pub const MSR_AMD_CPPC_CAP2: u32 = 0xc00102b2;
+pub const MSR_AMD_CPPC_REQ: u32 = 0xc00102b3;
+pub const MSR_AMD_CPPC_STATUS: u32 = 0xc00102b4;
+pub const MSR_AMD64_PERF_CNTR_GLOBAL_STATUS: u32 = 0xc0000300;
+pub const MSR_AMD64_PERF_CNTR_GLOBAL_CTL: u32 = 0xc0000301;
+pub const MSR_AMD64_PERF_CNTR_GLOBAL_STATUS_CLR: u32 = 0xc0000302;
+pub const MSR_AMD64_LBR_SELECT: u32 = 0xc000010e;
 pub const MSR_ZEN4_BP_CFG: u32 = 0xc001102e;
 pub const MSR_ZEN4_BP_CFG_SHARED_BTB_FIX_BIT: u32 = 0x5;
+pub const MSR_F19H_UMC_PERF_CTL: u32 = 0xc0010800;
+pub const MSR_F19H_UMC_PERF_CTR: u32 = 0xc0010801;
 pub const MSR_ZEN2_SPECTRAL_CHICKEN: u32 = 0xc00110e3;
 pub const MSR_F17H_IRPERF: u32 = 0xc00000e9;
 pub const MSR_F16H_L2I_PERF_CTL: u32 = 0xc0010230;
@@ -272,8 +336,11 @@ pub const MSR_FAM10H_MMIO_CONF_BASE: u32 = 0xc0010058;
 pub const MSR_FAM10H_NODE_ID: u32 = 0xc001100c;
 pub const MSR_K8_TOP_MEM1: u32 = 0xc001001a;
 pub const MSR_K8_TOP_MEM2: u32 = 0xc001001d;
-pub const MSR_K8_SYSCFG: u32 = 0xc0010010;
-pub const MSR_K8_SYSCFG_MEM_ENCRYPT_BIT: u32 = 0x17;
+pub const MSR_AMD64_SYSCFG: u32 = 0xc0010010;
+pub const MSR_AMD64_SYSCFG_MEM_ENCRYPT_BIT: u32 = 0x17;
+pub const MSR_AMD64_SYSCFG_SNP_EN_BIT: u32 = 0x18;
+pub const MSR_AMD64_SYSCFG_SNP_VMPL_EN_BIT: u32 = 0x19;
+pub const MSR_AMD64_SYSCFG_MFDM_BIT: u32 = 0x13;
 pub const MSR_K8_INT_PENDING_MSG: u32 = 0xc0010055;
 pub const MSR_K8_TSEG_ADDR: u32 = 0xc0010112;
 pub const MSR_K8_TSEG_MASK: u32 = 0xc0010113;
@@ -291,6 +358,7 @@ pub const MSR_K7_HWCR_SMMLOCK_BIT: u32 = 0x0;
 pub const MSR_K7_HWCR_IRPERF_EN_BIT: u32 = 0x1e;
 pub const MSR_K7_FID_VID_CTL: u32 = 0xc0010041;
 pub const MSR_K7_FID_VID_STATUS: u32 = 0xc0010042;
+pub const MSR_K7_HWCR_CPB_DIS_BIT: u32 = 0x19;
 pub const MSR_K6_WHCR: u32 = 0xc0000082;
 pub const MSR_K6_UWCCR: u32 = 0xc0000085;
 pub const MSR_K6_EPMR: u32 = 0xc0000086;
@@ -328,18 +396,25 @@ pub const MSR_IA32_FEAT_CTL: u32 = 0x3a;
 pub const MSR_IA32_TSC_ADJUST: u32 = 0x3b;
 pub const MSR_IA32_BNDCFGS: u32 = 0xd90;
 pub const MSR_IA32_BNDCFGS_RSVD: u32 = 0xffc;
+pub const MSR_IA32_XFD: u32 = 0x1c4;
+pub const MSR_IA32_XFD_ERR: u32 = 0x1c5;
 pub const MSR_IA32_XSS: u32 = 0xda0;
 pub const MSR_IA32_APICBASE: u32 = 0x1b;
 pub const MSR_IA32_APICBASE_BSP: u32 = 0x100;
 pub const MSR_IA32_APICBASE_ENABLE: u32 = 0x800;
 pub const MSR_IA32_APICBASE_BASE: u32 = 0xfffff000;
-pub const MSR_IA32_TSCDEADLINE: u32 = 0x6e0;
 pub const MSR_IA32_UCODE_WRITE: u32 = 0x79;
 pub const MSR_IA32_UCODE_REV: u32 = 0x8b;
+pub const MSR_IA32_SGXLEPUBKEYHASH0: u32 = 0x8c;
+pub const MSR_IA32_SGXLEPUBKEYHASH1: u32 = 0x8d;
+pub const MSR_IA32_SGXLEPUBKEYHASH2: u32 = 0x8e;
+pub const MSR_IA32_SGXLEPUBKEYHASH3: u32 = 0x8f;
 pub const MSR_IA32_SMM_MONITOR_CTL: u32 = 0x9b;
 pub const MSR_IA32_SMBASE: u32 = 0x9e;
 pub const MSR_IA32_PERF_STATUS: u32 = 0x198;
 pub const MSR_IA32_PERF_CTL: u32 = 0x199;
+pub const MSR_AMD_DBG_EXTN_CFG: u32 = 0xc000010f;
+pub const MSR_AMD_SAMP_BR_FROM: u32 = 0xc0010300;
 pub const MSR_IA32_MPERF: u32 = 0xe7;
 pub const MSR_IA32_APERF: u32 = 0xe8;
 pub const MSR_IA32_THERM_CONTROL: u32 = 0x19a;
@@ -410,6 +485,8 @@ pub const MSR_MISC_FEATURES_ENABLES_RING3MWAIT_BIT: u32 = 0x1;
 pub const MSR_IA32_TSC_DEADLINE: u32 = 0x6e0;
 pub const MSR_TSX_FORCE_ABORT: u32 = 0x10f;
 pub const MSR_TFA_RTM_FORCE_ABORT_BIT: u32 = 0x0;
+pub const MSR_TFA_TSX_CPUID_CLEAR_BIT: u32 = 0x1;
+pub const MSR_TFA_SDV_ENABLE_RTM_BIT: u32 = 0x2;
 pub const MSR_IA32_MCG_EAX: u32 = 0x180;
 pub const MSR_IA32_MCG_EBX: u32 = 0x181;
 pub const MSR_IA32_MCG_ECX: u32 = 0x182;
@@ -538,9 +615,22 @@ pub const MSR_IA32_VMX_TRUE_PROCBASED_CTLS: u32 = 0x48e;
 pub const MSR_IA32_VMX_TRUE_EXIT_CTLS: u32 = 0x48f;
 pub const MSR_IA32_VMX_TRUE_ENTRY_CTLS: u32 = 0x490;
 pub const MSR_IA32_VMX_VMFUNC: u32 = 0x491;
-pub const MSR_IA32_VMX_MISC_INTEL_PT: u32 = 0x4000;
-pub const MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS: u32 = 0x20000000;
-pub const MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE: u32 = 0x1f;
+pub const MSR_IA32_VMX_PROCBASED_CTLS3: u32 = 0x492;
+pub const MSR_IA32_L3_QOS_CFG: u32 = 0xc81;
+pub const MSR_IA32_L2_QOS_CFG: u32 = 0xc82;
+pub const MSR_IA32_QM_EVTSEL: u32 = 0xc8d;
+pub const MSR_IA32_QM_CTR: u32 = 0xc8e;
+pub const MSR_IA32_PQR_ASSOC: u32 = 0xc8f;
+pub const MSR_IA32_L3_CBM_BASE: u32 = 0xc90;
+pub const MSR_RMID_SNC_CONFIG: u32 = 0xca0;
+pub const MSR_IA32_L2_CBM_BASE: u32 = 0xd10;
+pub const MSR_IA32_MBA_THRTL_BASE: u32 = 0xd50;
+pub const MSR_IA32_MBA_BW_BASE: u32 = 0xc0000200;
+pub const MSR_IA32_SMBA_BW_BASE: u32 = 0xc0000280;
+pub const MSR_IA32_EVT_CFG_BASE: u32 = 0xc0000400;
 pub const MSR_VM_CR: u32 = 0xc0010114;
 pub const MSR_VM_IGNNE: u32 = 0xc0010115;
 pub const MSR_VM_HSAVE_PA: u32 = 0xc0010117;
+pub const MSR_IA32_HW_FEEDBACK_PTR: u32 = 0x17d0;
+pub const MSR_IA32_HW_FEEDBACK_CONFIG: u32 = 0x17d1;
+pub const MSR_IA32_XAPIC_DISABLE_STATUS: u32 = 0xbd;

src/vmm/src/arch/x86_64/generated/perf_event.rs

@@ -12,7 +12,8 @@
     clippy::undocumented_unsafe_blocks,
     missing_debug_implementations,
     clippy::tests_outside_test_module,
-    unsafe_op_in_unsafe_fn
+    unsafe_op_in_unsafe_fn,
+    clippy::redundant_static_lifetimes
 )]
 
 pub const MSR_ARCH_PERFMON_PERFCTR0: u32 = 0xc1;