feat: AMD support larger extended function entries

Updated the logic for setting the largest extended function entry, to
take the largest between host CPU value and 0x8000_0021. The minimum has
also been bumped to 0x8000_0021 to allow setting values regarding SRSO.

Signed-off-by: Jack Thomson <[email protected]>

Author: JackThomson2

docs/cpu_templates/cpuid-normalization.md

@@ -42,13 +42,13 @@ See also: [boot protocol settings](boot-protocol.md)
 
 ## AMD-specifc CPUID normalization
 
-| Description                                          |                Leaf                | Subleaf |      Register      | Bits  |
-| ---------------------------------------------------- | :--------------------------------: | :-----: | :----------------: | :---: |
-| Set IA32_ARCH_CAPABILITIES MSR as not present        |                0x7                 |    -    |        EDX         |  29   |
-| Update largest extended function entry to 0x8000001f |             0x80000000             |    -    |        EAX         | 31:0  |
-| Set topology extension bit                           |             0x80000001             |    -    |        ECX         |  22   |
-| Update brand string with a default AMD value         | 0x80000002, 0x80000003, 0x80000004 |    -    | EAX, EBX, ECX, EDX |  all  |
-| Update number of physical threads                    |             0x80000008             |    -    |        ECX         |  7:0  |
-| Update APIC ID size                                  |             0x80000008             |    -    |        ECX         | 15:12 |
-| Update cache topology information                    |             0x8000001d             |   all   |        all         |  all  |
-| Update extended APIC ID                              |             0x8000001e             |    -    |   EAX, EBX, ECX    |  all  |
+| Description                                                                             |                Leaf                | Subleaf |      Register      | Bits  |
+| --------------------------------------------------------------------------------------- | :--------------------------------: | :-----: | :----------------: | :---: |
+| Set IA32_ARCH_CAPABILITIES MSR as not present                                           |                0x7                 |    -    |        EDX         |  29   |
+| Update largest extended function entry to largest between host cpu entry and 0x80000021 |             0x80000000             |    -    |        EAX         | 31:0  |
+| Set topology extension bit                                                              |             0x80000001             |    -    |        ECX         |  22   |
+| Update brand string with a default AMD value                                            | 0x80000002, 0x80000003, 0x80000004 |    -    | EAX, EBX, ECX, EDX |  all  |
+| Update number of physical threads                                                       |             0x80000008             |    -    |        ECX         |  7:0  |
+| Update APIC ID size                                                                     |             0x80000008             |    -    |        ECX         | 15:12 |
+| Update cache topology information                                                       |             0x8000001d             |   all   |        all         |  all  |
+| Update extended APIC ID                                                                 |             0x8000001e             |    -    |   EAX, EBX, ECX    |  all  |

src/vmm/src/cpu_config/x86_64/cpuid/amd/normalize.rs

@@ -184,17 +184,23 @@ impl super::AmdCpuid {
     /// Update largest extended fn entry.
     #[allow(clippy::unwrap_used, clippy::unwrap_in_result)]
     fn update_largest_extended_fn_entry(&mut self) -> Result<(), NormalizeCpuidError> {
-        // KVM sets the largest extended function to 0x80000000. Change it to 0x8000001f
-        // Since we also use the leaf 0x8000001d (Extended Cache Topology).
+        // KVM sets the largest extended function to 0x80000000. Change it to the largest
+        // between host CPU and 0x8000_0021. AMD notes that hypervisors should synthesize the value
+        // of both IBPB_BRTYPE and SBPB stored in leaf 0x8000_0021.
+        //
+        // https://www.amd.com/content/dam/amd/en/documents/corporate/cr/speculative-return-stack-overflow-whitepaper.pdf
         let leaf_80000000 = self
             .get_mut(&CpuidKey::leaf(0x80000000))
             .ok_or(NormalizeCpuidError::MissingLeaf0x80000000)?;
 
+        // Take the largest between host cpu entry and 0x8000_0021
+        let extended_fn_entry = 0x8000_0021.max(get_range(cpuid(0x80000000).eax, 0..32));
+
         // Largest extended function. The largest CPUID extended function input value supported by
         // the processor implementation.
         //
         // l_func_ext: 0..32,
-        set_range(&mut leaf_80000000.result.eax, 0..32, 0x8000_001f).unwrap();
+        set_range(&mut leaf_80000000.result.eax, 0..32, extended_fn_entry).unwrap();
         Ok(())
     }