test: Skip MSR 0xE1 in test_cpu_config_dump_vs_actual

The MSR is R/W and guest OS modifies it after boot to control UMWAIT
feature.

Signed-off-by: Takahiro Itazuri <[email protected]>

Author: zulinx86

tests/integration_tests/functional/test_cpu_template_helper.py

@@ -188,6 +188,9 @@ def build_cpu_config_dict(cpu_config_path):
     0x48,
     # MSR_IA32_SMBASE is not accessible outside of System Management Mode.
     0x9E,
+    # MSR_IA32_UMWAIT_CONTROL is R/W MSR that guest OS modifies after boot to
+    # control UMWAIT feature.
+    0xE1,
     # MSR_IA32_TSX_CTRL is R/W MSR to disable Intel TSX feature as a mitigation
     # against TAA vulnerability.
     0x122,