Merge branch 'main' into legacy-unwrap

Author: ShadowCurse

.buildkite/common.py

@@ -14,15 +14,19 @@
 import subprocess
 from pathlib import Path
 
+# fmt: off
 DEFAULT_INSTANCES = [
-    "c5n.metal",  # Intel Skylake
-    "m5n.metal",  # Intel Cascade Lake
-    "m6i.metal",  # Intel Icelake
-    "m6a.metal",  # AMD Milan
-    "m7a.metal-48xl",  # AMD Genoa
-    "m6g.metal",  # Graviton2
-    "m7g.metal",  # Graviton3
+    "c5n.metal",      # Intel Skylake
+    "m5n.metal",      # Intel Cascade Lake
+    "m6i.metal",      # Intel Icelake
+    "m7i.metal-24xl", # Intel Sapphire Rapids
+    "m7i.metal-48xl", # Intel Sapphire Rapids
+    "m6a.metal",      # AMD Milan
+    "m7a.metal-48xl", # AMD Genoa
+    "m6g.metal",      # Graviton2
+    "m7g.metal",      # Graviton3
 ]
+# fmt: on
 
 DEFAULT_PLATFORMS = [
     ("al2", "linux_5.10"),

.buildkite/pipeline_cpu_template.py

@@ -30,6 +30,8 @@ class BkStep(str, Enum):
             "c5n.metal",
             "m5n.metal",
             "m6i.metal",
+            "m7i.metal-24xl",
+            "m7i.metal-48xl",
             "m6a.metal",
             "m7a.metal-48xl",
         ],
@@ -69,8 +71,9 @@ class BkStep(str, Enum):
             "c5n.metal",
             "m5n.metal",
             "m6i.metal",
+            "m7i.metal-24xl",
+            "m7i.metal-48xl",
             "m6a.metal",
-            "m7a.metal-48xl",
         ],
     },
 }

.buildkite/pipeline_cross.py

@@ -22,6 +22,8 @@
         "c5n.metal",
         "m5n.metal",
         "m6i.metal",
+        "m7i.metal-24xl",
+        "m7i.metal-48xl",
         "m6a.metal",
         "m7a.metal-48xl",
     ]

CHANGELOG.md

@@ -26,6 +26,10 @@ and this project adheres to
   WAITPKG CPUID bit in CPUID normalization. The feature enables a guest to put a
   physical processor into an idle state, which is undesirable in a FaaS
   environment since that is what the host wants to decide.
+- [#5142](https://github.com/firecracker-microvm/firecracker/pull/5142):
+  Clarified what CPU models are supported by each existing CPU template.
+  Firecracker exits with an error if a CPU template is used on an unsupported
+  CPU model.
 
 ### Deprecated
 
@@ -48,6 +52,11 @@ and this project adheres to
   the UFFD Unix domain socket open to prevent the race condition between the
   guest memory mappings message and the shutdown event that was sometimes
   causing arrival of an empty message on the UFFD handler side.
+- [#5143](https://github.com/firecracker-microvm/firecracker/pull/5143): Fixed
+  to report `process_startup_time_us` and `process_startup_time_cpu_us` metrics
+  for `api_server` right after the API server starts, while previously reported
+  before applying seccomp filter and starting the API server. Users may observe
+  a bit longer startup time metrics.
 
 ## [1.11.0]
 

Cargo.lock

@@ -135,6 +135,8 @@ We test all combinations of:
 | c5n.metal      | al2 linux_5.10   | ubuntu 24.04 | linux_5.10   |
 | m5n.metal      | al2023 linux_6.1 |              | linux_6.1    |
 | m6i.metal      |                  |              |              |
+| m7i.metal-24xl |                  |              |              |
+| m7i.metal-48xl |                  |              |              |
 | m6a.metal      |                  |              |              |
 | m7a.metal-48xl |                  |              |              |
 | m6g.metal      |                  |              |              |

README.md

@@ -48,14 +48,14 @@ Firecracker supports two types of CPU templates:
 
 At the moment the following set of static CPU templates are supported:
 
-| CPU template | CPU vendor | CPU model             |
-| ------------ | ---------- | --------------------- |
-| C3           | Intel      | any                   |
-| T2           | Intel      | any                   |
-| T2A          | AMD        | Milan                 |
-| T2CL         | Intel      | Cascade Lake or newer |
-| T2S          | Intel      | any                   |
-| V1N1         | ARM        | Neoverse V1           |
+| CPU template | CPU vendor | CPU model                       |
+| ------------ | ---------- | ------------------------------- |
+| C3           | Intel      | Skylake, Cascade Lake, Ice Lake |
+| T2           | Intel      | Skylake, Cascade Lake, Ice Lake |
+| T2A          | AMD        | Milan                           |
+| T2CL         | Intel      | Cascade Lake, Ice Lake          |
+| T2S          | Intel      | Skylake, Cascade Lake           |
+| V1N1         | ARM        | Neoverse V1                     |
 
 T2 and C3 templates are mapped as close as possible to AWS T2 and C3 instances
 in terms of CPU features. Note that on a microVM that is lauched with the C3
@@ -71,8 +71,8 @@ a performance assessment if they wish to use the T2S template. Note that
 Firecracker expects the host to always be running the latest version of the
 microcode.
 
-The T2CL template is mapped to be close to Intel Cascade Lake. It is not safe to
-use it on Intel CPUs older than Cascade Lake (such as Skylake).
+The T2CL template is mapped to be close to Intel Cascade Lake. It is only safe
+to use it on Intel Cascade Lake and Ice Lake.
 
 The only AMD template is T2A. It is considered safe to be used with AMD Milan.
 

docs/cpu_templates/cpu-templates.md

@@ -70,11 +70,6 @@ impl ApiServer {
         // Set the api payload size limit.
         server.set_payload_max_size(api_payload_limit);
 
-        // Store process start time metric.
-        process_time_reporter.report_start_time();
-        // Store process CPU start time metric.
-        process_time_reporter.report_cpu_start_time();
-
         // Load seccomp filters on the API thread.
         // Execution panics if filters cannot be loaded, use --no-seccomp if skipping filters
         // altogether is the desired behaviour.
@@ -86,6 +81,12 @@ impl ApiServer {
         }
 
         server.start_server().expect("Cannot start HTTP server");
+        info!("API server started.");
+
+        // Store process start time metric.
+        process_time_reporter.report_start_time();
+        // Store process CPU start time metric.
+        process_time_reporter.report_cpu_start_time();
 
         loop {
             let request_vec = match server.requests() {

src/firecracker/src/api_server/mod.rs

@@ -8,7 +8,7 @@ use std::sync::{Arc, Mutex};
 use std::thread;
 
 use event_manager::{EventOps, Events, MutEventSubscriber, SubscriberOps};
-use vmm::logger::{ProcessTimeReporter, error, warn};
+use vmm::logger::{ProcessTimeReporter, error, info, warn};
 use vmm::resources::VmResources;
 use vmm::rpc_interface::{
     ApiRequest, ApiResponse, BuildMicrovmFromRequestsError, PrebootApiController,
@@ -175,6 +175,7 @@ pub(crate) fn run_with_api(
             return Err(ApiServerError::FailedToBindAndRunHttpServer(err));
         }
     };
+    info!("Listening on API socket ({bind_path:?}).");
 
     let api_kill_switch_clone = api_kill_switch
         .try_clone()

src/firecracker/src/api_server_adapter.rs

@@ -2,7 +2,7 @@
 // SPDX-License-Identifier: Apache-2.0
 
 use std::arch::x86_64::__cpuid as host_cpuid;
-use std::cmp::{Eq, Ordering, PartialEq, PartialOrd};
+use std::cmp::{Eq, PartialEq};
 
 /// Structure representing x86_64 CPU model.
 #[derive(Debug, Eq, PartialEq)]
@@ -19,6 +19,42 @@ pub struct CpuModel {
     pub stepping: u8,
 }
 
+/// Family / Model / Stepping for Intel Skylake
+pub const SKYLAKE_FMS: CpuModel = CpuModel {
+    extended_family: 0x0,
+    extended_model: 0x5,
+    family: 0x6,
+    model: 0x5,
+    stepping: 0x4,
+};
+
+/// Family / Model / Stepping for Intel Cascade Lake
+pub const CASCADE_LAKE_FMS: CpuModel = CpuModel {
+    extended_family: 0x0,
+    extended_model: 0x5,
+    family: 0x6,
+    model: 0x5,
+    stepping: 0x7,
+};
+
+/// Family / Model / Stepping for Intel Ice Lake
+pub const ICE_LAKE_FMS: CpuModel = CpuModel {
+    extended_family: 0x0,
+    extended_model: 0x6,
+    family: 0x6,
+    model: 0xa,
+    stepping: 0x6,
+};
+
+/// Family / Model / Stepping for AMD Milan
+pub const MILAN_FMS: CpuModel = CpuModel {
+    extended_family: 0xa,
+    extended_model: 0x0,
+    family: 0xf,
+    model: 0x1,
+    stepping: 0x1,
+};
+
 impl CpuModel {
     /// Get CPU model from current machine.
     pub fn get_cpu_model() -> Self {
@@ -27,19 +63,6 @@ impl CpuModel {
         let eax = unsafe { host_cpuid(0x1) }.eax;
         CpuModel::from(&eax)
     }
-
-    /// Check if the current CPU model is Intel Cascade Lake or later.
-    pub fn is_at_least_cascade_lake(&self) -> bool {
-        let cascade_lake = CpuModel {
-            extended_family: 0,
-            extended_model: 5,
-            family: 6,
-            model: 5,
-            stepping: 7,
-        };
-
-        self >= &cascade_lake
-    }
 }
 
 impl From<&u32> for CpuModel {
@@ -54,59 +77,22 @@ impl From<&u32> for CpuModel {
     }
 }
 
-impl From<&CpuModel> for u32 {
-    fn from(cpu_model: &CpuModel) -> Self {
-        (u32::from(cpu_model.extended_family) << 20)
-            | (u32::from(cpu_model.extended_model) << 16)
-            | (u32::from(cpu_model.family) << 8)
-            | (u32::from(cpu_model.model) << 4)
-            | u32::from(cpu_model.stepping)
-    }
-}
-
-impl PartialOrd for CpuModel {
-    fn partial_cmp(&self, other: &Self) -> Option<Ordering> {
-        Some(u32::from(self).cmp(&u32::from(other)))
-    }
-}
-
-impl Ord for CpuModel {
-    fn cmp(&self, other: &Self) -> Ordering {
-        u32::from(self).cmp(&u32::from(other))
-    }
-}
-
 #[cfg(test)]
 mod tests {
     use super::*;
 
-    const SKYLAKE: CpuModel = CpuModel {
-        extended_family: 0,
-        extended_model: 5,
-        family: 6,
-        model: 5,
-        stepping: 4,
-    };
-
-    const CASCADE_LAKE: CpuModel = CpuModel {
-        extended_family: 0,
-        extended_model: 5,
-        family: 6,
-        model: 5,
-        stepping: 7,
-    };
-
     #[test]
     fn cpu_model_from() {
         let skylake_eax = 0x00050654;
-        assert_eq!(u32::from(&SKYLAKE), skylake_eax);
-        assert_eq!(CpuModel::from(&skylake_eax), SKYLAKE);
-    }
+        assert_eq!(CpuModel::from(&skylake_eax), SKYLAKE_FMS);
 
-    #[test]
-    fn cpu_model_ord() {
-        assert_eq!(SKYLAKE, SKYLAKE);
-        assert!(SKYLAKE < CASCADE_LAKE);
-        assert!(CASCADE_LAKE > SKYLAKE);
+        let cascade_lake_eax = 0x00050657;
+        assert_eq!(CpuModel::from(&cascade_lake_eax), CASCADE_LAKE_FMS);
+
+        let ice_lake_eax = 0x000606a6;
+        assert_eq!(CpuModel::from(&ice_lake_eax), ICE_LAKE_FMS);
+
+        let milan_eax = 0x00a00f11;
+        assert_eq!(CpuModel::from(&milan_eax), MILAN_FMS);
     }
 }