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+ # Boot protocol register settings
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+
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+ Firecracker makes certain modifications to the guest's registers
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+ regardless of whether a CPU template is used to comply with the boot protocol.
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+ If a CPU template is used the boot protocol settings are performed _ after_ the
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+ CPU template is applied. That means that if the CPU template configures CPUID
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+ bits used in the boot protocol settings, they will be overwritten.
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+
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+ See also: [ CPUID normalization] ( cpuid-normalization.md )
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+
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+ ## Boot protocol MSRs (x86_64 only)
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+
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+ On x86_64, the following MSRs are set to ` 0 ` :
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+
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+ - MSR_IA32_SYSENTER_CS
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+ - MSR_IA32_SYSENTER_ESP
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+ - MSR_IA32_SYSENTER_EIP
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+ - MSR_STAR
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+ - MSR_CSTAR
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+ - MSR_KERNEL_GS_BASE
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+ - MSR_SYSCALL_MASK
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+ - MSR_LSTAR
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+ - MSR_IA32_TSC
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+
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+ and MSR_IA32_MISC_ENABLE is set to ` 1 ` .
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+
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+ ## Boot protocol ARM registers (aarch64 only)
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+
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+ On aarch64, the following registers are set:
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+
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+ - PSTATE to PSR_MODE_EL1h | PSR_A_BIT | PSR_F_BIT | PSR_I_BIT | PSR_D_BIT
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+ - PC to kernel load address (vCPU0 only)
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+ - X0 to DTB/FDT address (vCPU0 only)
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