refactor(vmm): Rename constants for register modification

Rename the following constants to make it clear which register the bit
belongs to:
- `TSC_DEADLINE_BITINDEX` => `ECX_TSC_DEADLINE_BITINDEX`
- `HYPERVISOR_BITINDEX` => `ECX_HYPERVISOR_BITINDEX`

Signed-off-by: Takahiro Itazuri <[email protected]>

Author: zulinx86

src/vmm/src/cpu_config/x86_64/cpuid/normalize.rs

@@ -206,14 +206,14 @@ impl super::Cpuid {
         cpu_index: u8,
         cpu_count: u8,
     ) -> Result<(), FeatureInformationError> {
-        /// Flush a cache line size.
+        // Flush a cache line size.
         const EBX_CLFLUSH_CACHELINE: u32 = 8;
 
         // TSC-Deadline.
-        const TSC_DEADLINE_BITINDEX: u8 = 24;
+        const ECX_TSC_DEADLINE_BITINDEX: u8 = 24;
 
-        /// CPU is running on a hypervisor.
-        const HYPERVISOR_BITINDEX: u8 = 31;
+        // CPU is running on a hypervisor.
+        const ECX_HYPERVISOR_BITINDEX: u8 = 31;
 
         let leaf_1 = self
             .get_mut(&CpuidKey::leaf(0x1))
@@ -223,10 +223,10 @@ impl super::Cpuid {
         // operation using a TSC deadline value.
         //
         // tsc_deadline: 24,
-        set_bit(&mut leaf_1.result.ecx, TSC_DEADLINE_BITINDEX, true);
+        set_bit(&mut leaf_1.result.ecx, ECX_TSC_DEADLINE_BITINDEX, true);
 
         // Hypervisor bit
-        set_bit(&mut leaf_1.result.ecx, HYPERVISOR_BITINDEX, true);
+        set_bit(&mut leaf_1.result.ecx, ECX_HYPERVISOR_BITINDEX, true);
 
         // Initial APIC ID.
         //