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pci: remove unused code
We are vending PCI code taken from Cloud Hypervisor's implementation. There is code in there that we don't actually use. So drop it to reduce the dead code in the project. Signed-off-by: Babis Chalios <[email protected]>
1 parent 77b8d30 commit f691ed8

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4 files changed

+24
-204
lines changed

4 files changed

+24
-204
lines changed

‎src/pci/src/bus.rs‎

Lines changed: 2 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -11,13 +11,10 @@ use std::ops::DerefMut;
1111
use std::sync::{Arc, Barrier, Mutex};
1212

1313
use byteorder::{ByteOrder, LittleEndian};
14-
use vm_device::{Bus, BusDevice, BusDeviceSync};
14+
use vm_device::BusDevice;
1515

16-
use crate::configuration::{
17-
PciBarRegionType, PciBridgeSubclass, PciClassCode, PciConfiguration, PciHeaderType,
18-
};
16+
use crate::configuration::{PciBridgeSubclass, PciClassCode, PciConfiguration, PciHeaderType};
1917
use crate::device::{DeviceRelocation, Error as PciDeviceError, PciDevice};
20-
use crate::PciBarConfiguration;
2118

2219
const VENDOR_ID_INTEL: u16 = 0x8086;
2320
const DEVICE_ID_INTEL_VIRT_PCIE_HOST: u16 = 0x0d57;
@@ -123,40 +120,11 @@ impl PciBus {
123120
}
124121
}
125122

126-
pub fn register_mapping(
127-
&self,
128-
dev: Arc<dyn BusDeviceSync>,
129-
io_bus: &Bus,
130-
mmio_bus: &Bus,
131-
bars: Vec<PciBarConfiguration>,
132-
) -> Result<()> {
133-
for bar in bars {
134-
match bar.region_type() {
135-
PciBarRegionType::IoRegion => {
136-
io_bus
137-
.insert(dev.clone(), bar.addr(), bar.size())
138-
.map_err(PciRootError::PioInsert)?;
139-
}
140-
PciBarRegionType::Memory32BitRegion | PciBarRegionType::Memory64BitRegion => {
141-
mmio_bus
142-
.insert(dev.clone(), bar.addr(), bar.size())
143-
.map_err(PciRootError::MmioInsert)?;
144-
}
145-
}
146-
}
147-
Ok(())
148-
}
149-
150123
pub fn add_device(&mut self, device_id: u32, device: Arc<Mutex<dyn PciDevice>>) -> Result<()> {
151124
self.devices.insert(device_id, device);
152125
Ok(())
153126
}
154127

155-
pub fn remove_by_device(&mut self, device: &Arc<Mutex<dyn PciDevice>>) -> Result<()> {
156-
self.devices.retain(|_, dev| !Arc::ptr_eq(dev, device));
157-
Ok(())
158-
}
159-
160128
pub fn next_device_id(&mut self) -> Result<u32> {
161129
for (idx, device_id) in self.device_ids.iter_mut().enumerate() {
162130
if !(*device_id) {
@@ -167,28 +135,6 @@ impl PciBus {
167135

168136
Err(PciRootError::NoPciDeviceSlotAvailable)
169137
}
170-
171-
pub fn get_device_id(&mut self, id: usize) -> Result<()> {
172-
if id < NUM_DEVICE_IDS {
173-
if !self.device_ids[id] {
174-
self.device_ids[id] = true;
175-
Ok(())
176-
} else {
177-
Err(PciRootError::AlreadyInUsePciDeviceSlot(id))
178-
}
179-
} else {
180-
Err(PciRootError::InvalidPciDeviceSlot(id))
181-
}
182-
}
183-
184-
pub fn put_device_id(&mut self, id: usize) -> Result<()> {
185-
if id < NUM_DEVICE_IDS {
186-
self.device_ids[id] = false;
187-
Ok(())
188-
} else {
189-
Err(PciRootError::InvalidPciDeviceSlot(id))
190-
}
191-
}
192138
}
193139

194140
pub struct PciConfigIo {

‎src/pci/src/configuration.rs‎

Lines changed: 6 additions & 126 deletions
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ use serde::{Deserialize, Serialize};
1313
use vm_device::PciBarType;
1414

1515
use crate::device::BarReprogrammingParams;
16-
use crate::{MsixConfig, PciInterruptPin};
16+
use crate::MsixConfig;
1717

1818
// The number of 32bit registers in the config space, 4096 bytes.
1919
const NUM_CONFIGURATION_REGISTERS: usize = 1024;
@@ -22,7 +22,6 @@ const STATUS_REG: usize = 1;
2222
const STATUS_REG_CAPABILITIES_USED_MASK: u32 = 0x0010_0000;
2323
const BAR0_REG: usize = 4;
2424
const ROM_BAR_REG: usize = 12;
25-
const ROM_BAR_IDX: usize = 6;
2625
const BAR_IO_ADDR_MASK: u32 = 0xffff_fffc;
2726
const BAR_MEM_ADDR_MASK: u32 = 0xffff_fff0;
2827
const ROM_BAR_ADDR_MASK: u32 = 0xffff_f800;
@@ -33,8 +32,6 @@ const CAPABILITY_LIST_HEAD_OFFSET: usize = 0x34;
3332
const FIRST_CAPABILITY_OFFSET: usize = 0x40;
3433
const CAPABILITY_MAX_OFFSET: usize = 192;
3534

36-
const INTERRUPT_LINE_PIN_REG: usize = 15;
37-
3835
pub const PCI_CONFIGURATION_ID: &str = "pci_configuration";
3936

4037
/// Represents the types of PCI headers allowed in the configuration registers.
@@ -483,11 +480,11 @@ impl From<PciBarPrefetchable> for bool {
483480

484481
#[derive(Debug, Copy, Clone, Serialize, Deserialize)]
485482
pub struct PciBarConfiguration {
486-
addr: u64,
487-
size: u64,
488-
idx: usize,
489-
region_type: PciBarRegionType,
490-
prefetchable: PciBarPrefetchable,
483+
pub addr: u64,
484+
pub size: u64,
485+
pub idx: usize,
486+
pub region_type: PciBarRegionType,
487+
pub prefetchable: PciBarPrefetchable,
491488
}
492489

493490
#[derive(Debug)]
@@ -797,42 +794,6 @@ impl PciConfiguration {
797794
Ok(())
798795
}
799796

800-
/// Adds rom expansion BAR.
801-
pub fn add_pci_rom_bar(&mut self, config: &PciBarConfiguration, active: u32) -> Result<()> {
802-
let bar_idx = config.idx;
803-
let reg_idx = ROM_BAR_REG;
804-
805-
if self.rom_bar_used {
806-
return Err(Error::RomBarInUse(bar_idx));
807-
}
808-
809-
if !config.size.is_power_of_two() {
810-
return Err(Error::RomBarSizeInvalid(config.size));
811-
}
812-
813-
if bar_idx != ROM_BAR_IDX {
814-
return Err(Error::RomBarInvalid(bar_idx));
815-
}
816-
817-
let end_addr = config
818-
.addr
819-
.checked_add(config.size - 1)
820-
.ok_or(Error::RomBarAddressInvalid(config.addr, config.size))?;
821-
822-
if end_addr > u64::from(u32::MAX) {
823-
return Err(Error::RomBarAddressInvalid(config.addr, config.size));
824-
}
825-
826-
self.registers[reg_idx] = (config.addr as u32) | active;
827-
self.writable_bits[reg_idx] = ROM_BAR_ADDR_MASK;
828-
self.rom_bar_addr = self.registers[reg_idx];
829-
self.rom_bar_size =
830-
encode_32_bits_bar_size(config.size as u32).ok_or(Error::Encode32BarSize)?;
831-
self.rom_bar_used = true;
832-
833-
Ok(())
834-
}
835-
836797
/// Returns the address of the given BAR region.
837798
pub fn get_bar_addr(&self, bar_num: usize) -> u64 {
838799
let bar_idx = BAR0_REG + bar_num;
@@ -848,16 +809,6 @@ impl PciConfiguration {
848809
addr
849810
}
850811

851-
/// Configures the IRQ line and pin used by this device.
852-
pub fn set_irq(&mut self, line: u8, pin: PciInterruptPin) {
853-
// `pin` is 1-based in the pci config space.
854-
let pin_idx = (pin as u32) + 1;
855-
self.registers[INTERRUPT_LINE_PIN_REG] = (self.registers[INTERRUPT_LINE_PIN_REG]
856-
& 0xffff_0000)
857-
| (pin_idx << 8)
858-
| u32::from(line);
859-
}
860-
861812
/// Adds the capability `cap_data` to the list of capabilities.
862813
/// `cap_data` should include the two-byte PCI capability header (type, next),
863814
/// but not populate it. Correct values will be generated automatically based
@@ -940,10 +891,6 @@ impl PciConfiguration {
940891
}
941892
}
942893

943-
pub fn read_config_register(&self, reg_idx: usize) -> u32 {
944-
self.read_reg(reg_idx)
945-
}
946-
947894
pub fn detect_bar_reprogramming(
948895
&mut self,
949896
reg_idx: usize,
@@ -1074,73 +1021,6 @@ impl Default for PciBarConfiguration {
10741021
}
10751022
}
10761023

1077-
impl PciBarConfiguration {
1078-
pub fn new(
1079-
idx: usize,
1080-
size: u64,
1081-
region_type: PciBarRegionType,
1082-
prefetchable: PciBarPrefetchable,
1083-
) -> Self {
1084-
PciBarConfiguration {
1085-
idx,
1086-
addr: 0,
1087-
size,
1088-
region_type,
1089-
prefetchable,
1090-
}
1091-
}
1092-
1093-
#[must_use]
1094-
pub fn set_index(mut self, idx: usize) -> Self {
1095-
self.idx = idx;
1096-
self
1097-
}
1098-
1099-
#[must_use]
1100-
pub fn set_address(mut self, addr: u64) -> Self {
1101-
self.addr = addr;
1102-
self
1103-
}
1104-
1105-
#[must_use]
1106-
pub fn set_size(mut self, size: u64) -> Self {
1107-
self.size = size;
1108-
self
1109-
}
1110-
1111-
#[must_use]
1112-
pub fn set_region_type(mut self, region_type: PciBarRegionType) -> Self {
1113-
self.region_type = region_type;
1114-
self
1115-
}
1116-
1117-
#[must_use]
1118-
pub fn set_prefetchable(mut self, prefetchable: PciBarPrefetchable) -> Self {
1119-
self.prefetchable = prefetchable;
1120-
self
1121-
}
1122-
1123-
pub fn idx(&self) -> usize {
1124-
self.idx
1125-
}
1126-
1127-
pub fn addr(&self) -> u64 {
1128-
self.addr
1129-
}
1130-
1131-
pub fn size(&self) -> u64 {
1132-
self.size
1133-
}
1134-
1135-
pub fn region_type(&self) -> PciBarRegionType {
1136-
self.region_type
1137-
}
1138-
1139-
pub fn prefetchable(&self) -> PciBarPrefetchable {
1140-
self.prefetchable
1141-
}
1142-
}
1143-
11441024
#[cfg(test)]
11451025
mod tests {
11461026
use vm_memory::ByteValued;

‎src/vmm/src/device_manager/pci_mngr.rs‎

Lines changed: 5 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -89,28 +89,20 @@ impl PciDevices {
8989
virtio_device: &Arc<Mutex<VirtioPciDevice>>,
9090
) -> Result<(), PciManagerError> {
9191
for bar in &virtio_device.lock().expect("Poisoned lock").bar_regions {
92-
match bar.region_type() {
92+
match bar.region_type {
9393
PciBarRegionType::IoRegion => {
94-
debug!(
95-
"Inserting I/O BAR region: {:#x}:{:#x}",
96-
bar.addr(),
97-
bar.size()
98-
);
94+
debug!("Inserting I/O BAR region: {:#x}:{:#x}", bar.addr, bar.size);
9995
#[cfg(target_arch = "x86_64")]
10096
vm.pio_bus
101-
.insert(virtio_device.clone(), bar.addr(), bar.size())?;
97+
.insert(virtio_device.clone(), bar.addr, bar.size)?;
10298
#[cfg(target_arch = "aarch64")]
10399
log::error!("pci: We do not support I/O region allocation")
104100
}
105101
PciBarRegionType::Memory32BitRegion | PciBarRegionType::Memory64BitRegion => {
106-
debug!(
107-
"Inserting MMIO BAR region: {:#x}:{:#x}",
108-
bar.addr(),
109-
bar.size()
110-
);
102+
debug!("Inserting MMIO BAR region: {:#x}:{:#x}", bar.addr, bar.size);
111103
vm.common
112104
.mmio_bus
113-
.insert(virtio_device.clone(), bar.addr(), bar.size())?;
105+
.insert(virtio_device.clone(), bar.addr, bar.size)?;
114106
}
115107
}
116108
}

‎src/vmm/src/devices/virtio/transport/pci/device.rs‎

Lines changed: 11 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -918,11 +918,13 @@ impl PciDevice for VirtioPciDevice {
918918
(addr, region_type)
919919
};
920920

921-
let bar = PciBarConfiguration::default()
922-
.set_index(VIRTIO_COMMON_BAR_INDEX)
923-
.set_address(virtio_pci_bar_addr)
924-
.set_size(CAPABILITY_BAR_SIZE)
925-
.set_region_type(region_type);
921+
let bar = PciBarConfiguration {
922+
addr: virtio_pci_bar_addr,
923+
size: CAPABILITY_BAR_SIZE,
924+
idx: VIRTIO_COMMON_BAR_INDEX,
925+
region_type,
926+
prefetchable: pci::PciBarPrefetchable::NotPrefetchable,
927+
};
926928

927929
// The creation of the PCI BAR and its associated capabilities must
928930
// happen only during the creation of a brand new VM. When a VM is
@@ -948,8 +950,8 @@ impl PciDevice for VirtioPciDevice {
948950
mmio64_allocator: &mut AddressAllocator,
949951
) -> std::result::Result<(), PciDeviceError> {
950952
for bar in self.bar_regions.drain(..) {
951-
let range = RangeInclusive::new(bar.addr(), bar.addr() + bar.size()).unwrap();
952-
match bar.region_type() {
953+
let range = RangeInclusive::new(bar.addr, bar.addr + bar.size).unwrap();
954+
match bar.region_type {
953955
PciBarRegionType::Memory32BitRegion => {
954956
mmio32_allocator.free(&range);
955957
}
@@ -970,8 +972,8 @@ impl PciDevice for VirtioPciDevice {
970972
// We only update our idea of the bar in order to support free_bars() above.
971973
// The majority of the reallocation is done inside DeviceManager.
972974
for bar in self.bar_regions.iter_mut() {
973-
if bar.addr() == old_base {
974-
*bar = bar.set_address(new_base);
975+
if bar.addr == old_base {
976+
bar.addr = new_base;
975977
}
976978
}
977979

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