fix: MSR_SYSCALL_MASK changed in 6.1 guest kernel to 0x257fd5

Manciukic · pb8o · commit fff97dcacebc · 2024-08-21T16:16:21.000+02:00
This change updates the expected MSR value for MSR_SYSCALL_MASK
(0xc0000084) to 0x257fd5 for the 6.1 guest kernel.

Signed-off-by: Riccardo Mancini &lt;mancio@amazon.com&gt;
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_5.10host_6.1guest.csv
@@ -243,7 +243,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81600040
 0xc0000083,0xffffffff81601500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7ff85489f740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2A_AMD_MILAN_6.1host_6.1guest.csv
@@ -243,7 +243,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81800000
 0xc0000083,0xffffffff81801400
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7f99e723c500
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_5.10host_6.1guest.csv
@@ -461,7 +461,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81800040
 0xc0000083,0xffffffff81801500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7f6a7d9dd740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_CASCADELAKE_6.1host_6.1guest.csv
@@ -461,7 +461,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81600040
 0xc0000083,0xffffffff81601500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7fe9b31fd740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_5.10host_6.1guest.csv
@@ -461,7 +461,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81600040
 0xc0000083,0xffffffff81601500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7f8958489740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2CL_INTEL_ICELAKE_6.1host_6.1guest.csv
@@ -461,7 +461,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81800040
 0xc0000083,0xffffffff81801500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7fb8f2024740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_5.10host_6.1guest.csv
@@ -460,7 +460,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81600040
 0xc0000083,0xffffffff81601500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7f3ce0258740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_CASCADELAKE_6.1host_6.1guest.csv
@@ -460,7 +460,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81600040
 0xc0000083,0xffffffff81601500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7f03eb8b3740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_5.10host_6.1guest.csv
@@ -460,7 +460,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81600040
 0xc0000083,0xffffffff81601500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7fea39cd1740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_ICELAKE_6.1host_6.1guest.csv
@@ -460,7 +460,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81600040
 0xc0000083,0xffffffff81601500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7f1666205740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_5.10host_6.1guest.csv
@@ -460,7 +460,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81800040
 0xc0000083,0xffffffff81801500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7ff086f4a740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
diff --git a/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_6.1guest.csv b/tests/data/msr/msr_list_T2S_INTEL_SKYLAKE_6.1host_6.1guest.csv
@@ -460,7 +460,7 @@ MSR_ADDR,VALUE
 0xc0000081,0x23001000000000
 0xc0000082,0xffffffff81800040
 0xc0000083,0xffffffff81801500
-0xc0000084,0x47700
+0xc0000084,0x257fd5
 0xc0000100,0x7f4e02611740
 0xc0000101,0xffff88803ec00000
 0xc0000102,0x0
