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bchalios
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firecracker-microvm:feature/pcie
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bchalios:msix_assertions
Jul 29, 2025
Merged
Msix assertions #5334
bchalios
merged 6 commits into
firecracker-microvm:feature/pcie
from
bchalios:msix_assertions
Jul 29, 2025
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Codecov Report❌ Patch coverage is
Additional details and impacted files@@ Coverage Diff @@
## feature/pcie #5334 +/- ##
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+ Coverage 80.23% 80.35% +0.12%
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Files 265 265
Lines 30817 30821 +4
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+ Hits 24725 24767 +42
+ Misses 6092 6054 -38
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Manciukic
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Probably missed during a rebase of `feature/pcie` on top of `main` branch. Signed-off-by: Babis Chalios <[email protected]>
It is true that writes/reads of an MSI-X table are either 32 or 64 bits long. However, we do check for this invariant in the `match` expression just after the assertion. If the invariant is not held (the guest tried to read/write with an invalid length) we just print an error and continue. This branch of the `match` block is never reached due to the assertion itself. To simplify things, just remove the assertion and let the `match` block logic handle invalid memory accesses. This should also help us better fuzz the bus accesses. Do add a check that the data access is up to 8 bytes long. These are all MMIO or Port IO accesses and they can't be bigger than 8 bytes. So this assertion should never fail in production (unless there's a KVM bug or we try to run Firecracker in some architecture that allows more than 64bit memory accesses). Signed-off-by: Babis Chalios <[email protected]>
We were using a Hashmap to store the GSIs that were used by the vectors of an MSI-X group. These vectors were always indexed starting by 0, so we can just use a simple Vec. Signed-off-by: Babis Chalios <[email protected]>
We are using a HashMap to track the interrupt routes we use in the system. The index to the HashMap is the GSI of the interrupt route. We know the maximum number of GSIs we have available so pre-allocate the space for the HashMap to avoid reallocations at runtime. Signed-off-by: Babis Chalios <[email protected]>
Fix a bug in the common VirtIO configuration for PCI transport where we would use `queue_select` to read the queue's MSI vector without validating it matches a valid queue. This could lead in panics when accessing the `msix_queue` array. The spec states that in such cases we should return `NO_VECTOR` (0xffff), so do that. Signed-off-by: Babis Chalios <[email protected]>
We were shifting by the wrong number of bits for 2-byte accesses. Signed-off-by: Babis Chalios <[email protected]>
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Manciukic
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Changes
Various fixes in the PCI code:
HashMap
that was tracking objects index by integers starting from 0. Use aVec
instead.HashMap
used to track interrupt routes to the maximum possible interrupt number (considering IRQs and MSIs) we can have.License Acceptance
By submitting this pull request, I confirm that my contribution is made under
the terms of the Apache 2.0 license. For more information on following Developer
Certificate of Origin and signing off your commits, please check
CONTRIBUTING.md
.PR Checklist
tools/devtool checkbuild --all
to verify that the PR passesbuild checks on all supported architectures.
tools/devtool checkstyle
to verify that the PR passes theautomated style checks.
how they are solving the problem in a clear and encompassing way.
in the PR.
CHANGELOG.md
.Runbook for Firecracker API changes.
integration tests.
TODO
.rust-vmm
.