Fix large cluster read and writes

Author: ThadHouse

integration/src/main.rs

@@ -26,6 +26,12 @@ fn test_case<T: PartialEq + std::fmt::Debug>(test_case_name: &str, actual: T, ex
     }
 }
 
+#[cfg(target_arch = "arm")]
+const RESOURCE: &str = "RIO0";
+
+#[cfg(not(target_arch = "arm"))]
+const RESOURCE: &str = "rio://172.22.11.2/RIO0";
+
 #[allow(overflowing_literals)]
 fn main() -> Result<(), ni_fpga::Error> {
     let mut tmp_bitfile = NamedTempFile::new().unwrap();
@@ -34,7 +40,7 @@ fn main() -> Result<(), ni_fpga::Error> {
     let session = Session::open(
         tmp_bitfile.path().to_str().unwrap(),
         "D08F17F77A45A5692FA2342C6B86E0EE",
-        "RIO0",
+        RESOURCE,
     )?;
 
     test_case("read plain U8", session.read::<u8>(98306)?, 0b00000001);
@@ -98,15 +104,12 @@ fn main() -> Result<(), ni_fpga::Error> {
         session.read::<TestCluster>(98360)?,
         TestCluster { b: false, u: 1337 },
     );
-    // TODO: Investigate cluster array memory layout in order to fix this test.
-    // The expected array may be incorrect here, I don't exactly remember what I used for the
-    // fixture bitfile before my LabView FPGA trial expired.
     test_case(
         "read cluster array",
-        session.read::<[TestCluster; 2]>(98360)?,
+        session.read::<[TestCluster; 2]>(98364)?,
         [
-            TestCluster { b: true, u: 255 },
-            TestCluster { b: false, u: 1337 },
+            TestCluster { b: true, u: 1234 },
+            TestCluster { b: false, u: 5678 },
         ],
     );
 

ni-fpga/src/session.rs

@@ -44,10 +44,16 @@ impl Session {
             )
         });
         match status {
-            Status::Success => Ok(Datatype::unpack(
-                &FpgaBits::from_slice(&buffer)
-                    [((T::SIZE_IN_BITS - 1) / 8 + 1) * 8 - T::SIZE_IN_BITS..],
-            )?),
+            Status::Success => {
+                let slice_start = if (T::SIZE_IN_BITS - 1) / 8 + 1 <= 4 {
+                    ((T::SIZE_IN_BITS - 1) / 8 + 1) * 8 - T::SIZE_IN_BITS
+                } else {
+                    0
+                };
+                Ok(Datatype::unpack(
+                    &FpgaBits::from_slice(&buffer)[slice_start..],
+                )?)
+            }
             _ => Err(Error::FPGA(status)),
         }
     }
@@ -56,9 +62,13 @@ impl Session {
         [u8; (T::SIZE_IN_BITS - 1) / 8 + 1]: Sized,
     {
         let mut buffer = [0u8; (T::SIZE_IN_BITS - 1) / 8 + 1];
+        let slice_start = if (T::SIZE_IN_BITS - 1) / 8 + 1 <= 4 {
+            ((T::SIZE_IN_BITS - 1) / 8 + 1) * 8 - T::SIZE_IN_BITS
+        } else {
+            0
+        };
         Datatype::pack(
-            &mut FpgaBits::from_slice_mut(&mut buffer)
-                [((T::SIZE_IN_BITS - 1) / 8 + 1) * 8 - T::SIZE_IN_BITS..],
+            &mut FpgaBits::from_slice_mut(&mut buffer)[slice_start..],
             data,
         )?;
         let status = Status::from(unsafe {