fix: correct various typos (bytecodealliance#12807)

Signed-off-by: Ho Kim <ho.kim@ulagbulag.io>

Author: HoKim98

cranelift/assembler-x64/meta/src/generate/format.rs

@@ -25,7 +25,7 @@ enum ModRmStyle {
     },
 
     /// Same as `RegMem` above except that this is also used for VEX-encoded
-    /// instructios with "/is4" which indicates that the 4th register operand
+    /// instructions with "/is4" which indicates that the 4th register operand
     /// is encoded in a byte after the ModR/M byte.
     RegMemIs4 {
         reg: ModRmReg,

cranelift/bforest/src/map.rs

@@ -239,7 +239,7 @@ where
         }
     }
 
-    /// Iterate over the enties within the given range.
+    /// Iterate over the entries within the given range.
     pub fn range<'a, R, C>(
         &'a self,
         range: R,

cranelift/bforest/src/set.rs

@@ -544,7 +544,7 @@ mod tests {
     // Level 1: 1 root
     // Level 2: 8 inner
     // Level 3: 64 inner
-    // Level 4: 512 leafs, up to 7680 elements
+    // Level 4: 512 leaves, up to 7680 elements
     //
     // A 3-level tree can hold at most 960 elements.
     fn dense4l(f: &mut SetForest<i32>) -> Set<i32> {

cranelift/codegen/src/egraph/mod.rs

@@ -1057,7 +1057,7 @@ impl<'a> EgraphPass<'a> {
 /// Implementation of external-context equality and hashing on
 /// InstructionData. This allows us to deduplicate instructions given
 /// some context that lets us see its value lists, so we don't need to
-/// store arguments inline in the `InstuctionData` (or alongside it in
+/// store arguments inline in the `InstructionData` (or alongside it in
 /// some newly-defined key type) in all cases.
 struct GVNContext<'a> {
     value_lists: &'a ValueListPool,

cranelift/codegen/src/inline.rs

@@ -7,7 +7,7 @@
 //! have been marked the equivalent of `#[inline(never)]`, etc... Only the
 //! Cranelift user can understand these aspects of the full compilation
 //! pipeline, and these things can be very different between (say) Wasmtime and
-//! `cg_clif`. Therefore, this module does not attempt to define hueristics for
+//! `cg_clif`. Therefore, this module does not attempt to define heuristics for
 //! when inlining a particular call is likely beneficial. This module only
 //! provides hooks for the Cranelift user to define whether a given call should
 //! be inlined or not, and the mechanics to inline a callee into a particular
@@ -60,7 +60,7 @@ pub trait Inline {
     /// A hook invoked for each direct call instruction in a function, whose
     /// result determines whether Cranelift should inline a given call.
     ///
-    /// The Cranelift user is responsible for defining their own hueristics and
+    /// The Cranelift user is responsible for defining their own heuristics and
     /// deciding whether inlining the call is beneficial.
     ///
     /// When returning a function and directing Cranelift to inline its body

cranelift/codegen/src/isa/aarch64/inst/imms.rs

@@ -602,7 +602,7 @@ impl MoveWideConst {
         None
     }
 
-    /// Create a `MoveWideCosnt` from a given shift, if possible.
+    /// Create a `MoveWideConst` from a given shift, if possible.
     pub fn maybe_with_shift(imm: u16, shift: u8) -> Option<MoveWideConst> {
         let shift_enc = shift / 16;
         if shift_enc > 3 {

cranelift/codegen/src/isa/pulley_shared/abi.rs

@@ -165,7 +165,7 @@ where
 
     fn gen_load_stack(mem: StackAMode, into_reg: Writable<Reg>, ty: Type) -> Self::I {
         let mut flags = MemFlags::trusted();
-        // Stack loads/stores of vectors always use little-endianess to avoid
+        // Stack loads/stores of vectors always use little-endianness to avoid
         // implementing a byte-swap of vectors on big-endian platforms.
         if ty.is_vector() {
             flags.set_endianness(ir::Endianness::Little);
@@ -175,7 +175,7 @@ where
 
     fn gen_store_stack(mem: StackAMode, from_reg: Reg, ty: Type) -> Self::I {
         let mut flags = MemFlags::trusted();
-        // Stack loads/stores of vectors always use little-endianess to avoid
+        // Stack loads/stores of vectors always use little-endianness to avoid
         // implementing a byte-swap of vectors on big-endian platforms.
         if ty.is_vector() {
             flags.set_endianness(ir::Endianness::Little);

cranelift/codegen/src/isa/pulley_shared/inst.isle

@@ -356,7 +356,7 @@
   ;; Next see if the `oob` and `raw_addr` combination match. This will attempt
   ;; extract a full bounds check from these values. If everything succeeds the
   ;; final step is then to extract an 8-bit offset of the load/store operation,
-  ;; if appplicable, assuming that the constants used in various places all line
+  ;; if applicable, assuming that the constants used in various places all line
   ;; up just right.
   (if-let (OobSelect.All base bound wasm_addr access_size_plus_offset)
     (wasm_oob_select oob host_addr))

cranelift/codegen/src/isa/pulley_shared/inst/emit.rs

@@ -125,7 +125,7 @@ fn pulley_emit<P>(
     P: PulleyTargetKind,
 {
     match inst {
-        // Pseduo-instructions that don't actually encode to anything.
+        // Pseudo-instructions that don't actually encode to anything.
         Inst::Args { .. } | Inst::Rets { .. } | Inst::DummyUse { .. } => {}
 
         Inst::TrapIf { cond, code } => {

cranelift/codegen/src/isa/riscv64/inst_vector.isle

@@ -1735,7 +1735,7 @@
 ;; Builds a vector mask corresponding to the FloatCC operation.
 ;;
 ;; Recursion: recursive rules implement some condition codes in terms of a
-;; smaller set of primtives, which recursive rules would not apply to twice.
+;; smaller set of primitives, which recursive rules would not apply to twice.
 (decl rec gen_fcmp_mask (Type FloatCC Value Value) VReg)
 
 ;; FloatCC.Equal