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| 1 | +/* |
| 2 | + * Copyright (c) 2020-2023, NVIDIA CORPORATION. All rights reserved. |
| 3 | + * |
| 4 | + * Licensed under the Apache License, Version 2.0 (the "License"); |
| 5 | + * you may not use this file except in compliance with the License. |
| 6 | + * You may obtain a copy of the License at |
| 7 | + * |
| 8 | + * http://www.apache.org/licenses/LICENSE-2.0 |
| 9 | + * |
| 10 | + * Unless required by applicable law or agreed to in writing, software |
| 11 | + * distributed under the License is distributed on an "AS IS" BASIS, |
| 12 | + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
| 13 | + * See the License for the specific language governing permissions and |
| 14 | + * limitations under the License. |
| 15 | + */ |
| 16 | +#include <ATen/cuda/EmptyTensor.h> |
| 17 | +#include <cuda_fp16.h> |
| 18 | + |
| 19 | +#include <cstddef> |
| 20 | +#include <cstdint> |
| 21 | +#include <functional> |
| 22 | +#include <type_traits> |
| 23 | +#include <vector> |
| 24 | + |
| 25 | +#include "flashinfer/gemm/cutlass_gemm_configs.h" |
| 26 | +#include "flashinfer/gemm/fp8_gemm_cutlass.h" |
| 27 | +#include "flashinfer/gemm/fp8_gemm_cutlass_template.h" |
| 28 | +#include "pytorch_extension_utils.h" |
| 29 | + |
| 30 | +using flashinfer::gemm::ClusterShape; |
| 31 | +using flashinfer::gemm::CutlassFp8GemmRunner; |
| 32 | +using flashinfer::gemm::CutlassFp8GemmRunnerInterface; |
| 33 | +using flashinfer::gemm::CutlassGemmConfig; |
| 34 | +using flashinfer::gemm::CutlassTileConfigSM100; |
| 35 | +using flashinfer::gemm::EpilogueScheduleType; |
| 36 | +using flashinfer::gemm::MainloopScheduleType; |
| 37 | + |
| 38 | +namespace flashinfer { |
| 39 | +namespace gemm { |
| 40 | +template class CutlassFp8GemmRunner<__nv_bfloat16>; |
| 41 | +template class CutlassFp8GemmRunner<half>; |
| 42 | +} // namespace gemm |
| 43 | +} // namespace flashinfer |
| 44 | + |
| 45 | +namespace torch_ext { |
| 46 | + |
| 47 | +namespace { |
| 48 | + |
| 49 | +CutlassGemmConfig getFp8GemmConfig(int64_t m, int64_t n, int64_t k, int64_t tactic) { |
| 50 | + auto getCutlassFp8GemmConfigs = []() { |
| 51 | + CutlassFp8GemmRunner<__nv_bfloat16> gemmRunner; |
| 52 | + return gemmRunner.getConfigs(); |
| 53 | + }; |
| 54 | + static std::vector<CutlassGemmConfig> globalConfigs = getCutlassFp8GemmConfigs(); |
| 55 | + TORCH_CHECK(tactic >= 0 && tactic < globalConfigs.size(), "tactic must be between 0 and ", |
| 56 | + globalConfigs.size()); |
| 57 | + return globalConfigs[tactic]; |
| 58 | +} |
| 59 | + |
| 60 | +template <typename T> |
| 61 | +void runGemm(at::Tensor& out, at::Tensor const& mat1, at::Tensor const& mat2, |
| 62 | + at::Tensor const& scale, int64_t m, int64_t n, int64_t k, int64_t b, |
| 63 | + CutlassGemmConfig const& gemmConfig, at::Tensor workspace_buffer) { |
| 64 | + CutlassFp8GemmRunner<T> gemmRunner; |
| 65 | + |
| 66 | + int64_t const required_workspace_size = gemmRunner.getWorkspaceSize(m, n, k); |
| 67 | + int64_t const provided_workspace_size = |
| 68 | + workspace_buffer.numel() * workspace_buffer.element_size(); |
| 69 | + |
| 70 | + auto runKernel = [&](void* workspace) { |
| 71 | + gemmRunner.gemm(reinterpret_cast<__nv_fp8_e4m3 const*>(mat1.const_data_ptr()), |
| 72 | + reinterpret_cast<__nv_fp8_e4m3 const*>(mat2.const_data_ptr()), |
| 73 | + reinterpret_cast<float const*>(scale.const_data_ptr()), out.data_ptr(), m, n, k, |
| 74 | + b, gemmConfig, reinterpret_cast<char*>(workspace), required_workspace_size, |
| 75 | + at::cuda::getCurrentCUDAStream(mat1.get_device())); |
| 76 | + }; |
| 77 | + |
| 78 | + if (provided_workspace_size < required_workspace_size) { |
| 79 | + at::Tensor new_workspace = at::detail::empty_cuda( |
| 80 | + {required_workspace_size}, at::ScalarType::Char, mat1.device(), std::nullopt); |
| 81 | + |
| 82 | + runKernel(new_workspace.data_ptr()); |
| 83 | + } else { |
| 84 | + runKernel(workspace_buffer.data_ptr()); |
| 85 | + } |
| 86 | +} |
| 87 | + |
| 88 | +at::Tensor fp8_bmm_impl(at::Tensor const& mat1, at::Tensor const& mat2, at::Tensor const& scale, |
| 89 | + at::Tensor out, at::Tensor workspace_buffer, int64_t tactic) { |
| 90 | + CHECK_INPUT(mat1); |
| 91 | + CHECK_INPUT(mat2); |
| 92 | + |
| 93 | + int mat2_k_scale = 1; |
| 94 | + |
| 95 | + int64_t m, n, k, b; |
| 96 | + if (mat1.dim() == 2) { |
| 97 | + TORCH_CHECK(mat2.dim() == 2, "mat2 must be a matrix"); |
| 98 | + TORCH_CHECK(mat1.sizes()[1] == mat2.sizes()[1] * mat2_k_scale, |
| 99 | + "mat1 and mat2 shapes cannot be multiplied (", mat1.sizes()[0], "x", |
| 100 | + mat1.sizes()[1], " and ", mat2.sizes()[0], "x", mat2.sizes()[1], ")"); |
| 101 | + m = mat1.sizes()[0]; |
| 102 | + n = mat2.sizes()[0]; |
| 103 | + k = mat2.sizes()[1]; |
| 104 | + b = 1; |
| 105 | + } else if (mat1.dim() == 3) { |
| 106 | + TORCH_CHECK(mat2.dim() == 3, "mat2 must be a batch of matrices"); |
| 107 | + TORCH_CHECK(mat1.sizes()[0] == mat2.sizes()[0], "mat1 and mat2 must have the same batch size (", |
| 108 | + mat1.sizes()[0], " and ", mat2.sizes()[0], ")"); |
| 109 | + TORCH_CHECK(mat1.sizes()[2] == mat2.sizes()[2] * mat2_k_scale, |
| 110 | + "mat1 and mat2 shapes cannot be multiplied (", mat1.sizes()[1], "x", |
| 111 | + mat1.sizes()[2], " and ", mat2.sizes()[1], "x", mat2.sizes()[2], ")"); |
| 112 | + m = mat1.sizes()[1]; |
| 113 | + n = mat2.sizes()[1]; |
| 114 | + k = mat2.sizes()[2]; |
| 115 | + b = mat1.sizes()[0]; |
| 116 | + } else { |
| 117 | + C10_THROW_ERROR(NotImplementedError, "mat1 must be a matrix or a batch of matrices"); |
| 118 | + } |
| 119 | + |
| 120 | + // No heuristic for now, we rely on the autotuner to select the best tactic. |
| 121 | + if (tactic == -1) { |
| 122 | + tactic = 0; |
| 123 | + } |
| 124 | + auto config = getFp8GemmConfig(m, n, k, tactic); |
| 125 | + |
| 126 | + // Validate out dimensions |
| 127 | + std::vector<int64_t> out_shape = |
| 128 | + mat1.dim() == 2 ? std::vector<int64_t>{m, n} : std::vector<int64_t>{b, m, n}; |
| 129 | + TORCH_CHECK(out.dim() == out_shape.size(), "out must have ", out_shape.size(), |
| 130 | + " dimensions, but got ", out.dim()); |
| 131 | + for (int i = 0; i < out_shape.size(); ++i) { |
| 132 | + TORCH_CHECK(out.sizes()[i] == out_shape[i], "out shape mismatch at dimension ", i, |
| 133 | + ": expected ", out_shape[i], ", got ", out.sizes()[i]); |
| 134 | + } |
| 135 | + |
| 136 | + switch (out.scalar_type()) { |
| 137 | + case at::ScalarType::Half: |
| 138 | + runGemm<half>(out, mat1, mat2, scale, m, n, k, b, config, workspace_buffer); |
| 139 | + break; |
| 140 | + case at::ScalarType::BFloat16: |
| 141 | + runGemm<__nv_bfloat16>(out, mat1, mat2, scale, m, n, k, b, config, workspace_buffer); |
| 142 | + break; |
| 143 | + default: |
| 144 | + TORCH_CHECK(false, "out_dtype must be one of fp16/bf16."); |
| 145 | + } |
| 146 | + return out; |
| 147 | +} |
| 148 | + |
| 149 | +} // namespace |
| 150 | + |
| 151 | +at::Tensor fp8_gemm(at::Tensor const& mat1, at::Tensor const& mat2, at::Tensor const& scale, |
| 152 | + at::Tensor out, at::Tensor workspace_buffer, int64_t tactic) { |
| 153 | + return fp8_bmm_impl(mat1, mat2, scale, out, workspace_buffer, tactic); |
| 154 | +} |
| 155 | + |
| 156 | +int64_t fp8_gemm_tactic_num() { |
| 157 | + auto getCutlassConfigs = []() { |
| 158 | + CutlassFp8GemmRunner<__nv_bfloat16> gemmRunner; |
| 159 | + return gemmRunner.getConfigs(); |
| 160 | + }; |
| 161 | + static int64_t totalTactics = getCutlassConfigs().size(); |
| 162 | + return totalTactics; |
| 163 | +} |
| 164 | + |
| 165 | +} // namespace torch_ext |
| 166 | + |
| 167 | +TORCH_LIBRARY_FRAGMENT(TORCH_EXTENSION_NAME, m) { |
| 168 | + m.def("fp8_gemm", &torch_ext::fp8_gemm); |
| 169 | + m.def("fp8_gemm_tactic_num", &torch_ext::fp8_gemm_tactic_num); |
| 170 | +} |
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