rockchip: rk3576: Properly handle USB controller takeover from BootROM

When booting via USB download mode (Maskrom), the BootROM leaves the
USB3OTG0 controller in an active state. U-Boot must properly reset
the controller before reinitializing it for fastboot or other USB
gadget functions.

Changes:
1. Detect USB boot source using read_brom_bootsource_id()
2. When booted from USB:
   - Assert USB3OTG0 reset via TOP_CRU_SOFTRST_CON47
   - Wait 1ms for reset to complete
   - Deassert reset
   - Wait 1ms for controller to stabilize
   - Configure USB_GRF for proper operation
3. When booted from other sources:
   - Keep existing behavior of disabling U3 port initially
     (USBDP PHY driver enables it later when needed)

Also update rk3576-evb1-v10.dts to set dr_mode = "peripheral" for
usb_drd0_dwc3 to support fastboot gadget mode by default.

Without this fix, USB fastboot fails when U-Boot is loaded via
Maskrom USB download because the controller state is inconsistent.

Change-Id: e22b349e-fdde-40e8-a991-b3a49e37e645
Signed-off-by: Anton Burticica <mouse@ya.ru>

Author: ya-mouse

arch/arm/mach-rockchip/rk3576/rk3576.c

@@ -7,6 +7,7 @@
 
 #include <dm.h>
 #include <misc.h>
+#include <linux/delay.h>
 #include <asm/armv8/mmu.h>
 #include <asm/arch-rockchip/bootrom.h>
 #include <asm/arch-rockchip/hardware.h>
@@ -39,6 +40,10 @@
 #define USB_GRF_BASE		0x2601E000
 #define USB3OTG0_CON1		0x0030
 
+#define TOP_CRU_BASE		0x27200000
+#define TOP_CRU_SOFTRST_CON47	0x0abc
+
+
 enum {
 	BROM_BOOTSOURCE_FSPI0 = 3,
 	BROM_BOOTSOURCE_FSPI1_M1 = 6,
@@ -190,8 +195,16 @@ int arch_cpu_init(void)
 	 */
 	writel(0xffffff00, SYS_SGRF_BASE + SYS_SGRF_SOC_CON20);
 
-	/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
-	writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+	if (read_brom_bootsource_id() == BROM_BOOTSOURCE_USB) {
+		writel(0x00200020, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON47);
+		udelay(1000);
+		writel(0x00200000, TOP_CRU_BASE + TOP_CRU_SOFTRST_CON47);
+		udelay(1000);
+		writel(0x000c0008, USB_GRF_BASE + USB3OTG0_CON1);
+	} else {
+		/* Disable USB3OTG0 U3 port, later enabled by USBDP PHY driver */
+		writel(0xffff0188, USB_GRF_BASE + USB3OTG0_CON1);
+	}
 
 	return 0;
 }

dts/upstream/src/arm64/rockchip/rk3576-evb1-v10.dts

@@ -914,7 +914,7 @@
 };
 
 &usb_drd0_dwc3 {
-	dr_mode = "host";
+	dr_mode = "peripheral";
 	status = "okay";
 };