DigME/DigME.tex at main · flurin-b/DigME · GitHub

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% ========================================= TEMPLATE INFO ========================================
%
% Author:       P4ntomime
% Version:      1.0.0
% Last updated: 2024-02-18
% Brief:        A LaTeX template for summaries. See README.md for more information.
%
% ================================================================================================
\documentclass[8pt, a4paper, twoside]{extarticle}
% Font size:    8pt
% Paper size:   A4
% style:        twoside (needed, so odd and even pages have different margins)
% orientation:  portrait. (use 'landscape' for landscape orientation)


% ========================================= DOCUMENT INFO =========================================
\def\title{Digital Microelectronics}                            % title
\def\shorttitle{DigME}                                          % short title (displayed as PDF title)
\def\dozent{Prof. Dr. Paul Zbinden}                             % lecturer
\def\semester{HS 2024}                                          % semester
\def\author{Flurin Brechbühler, Laurin Heitzer, Simone Stitz}   % authors
\def\repo{https://github.com/flurin-b/DigME}                    % repository link
\def\version{1.0.\today}                                        % version
\def\pagelimit{20}                                              % page limit -> causes pages after limit to be red
\def\titleoption{ultra compact}                                 % options: compact, normal
\def\enableToC{true}

% ================================= PACKAGES, SETUP AND COMMANDS ==================================
\input{preamble.tex}

\newcommand{\mytext}[1]{\quad\text{#1}\quad}

% =========================================== DOCUMENT ============================================
\begin{document}
    \begin{layout}
        \part{DigMe}
        \input{sections/01_how_to_design_an_soc.tex}
        \input{sections/02_constraints.tex}
        \input{sections/03_system_level_vhdl.tex}
        \input{sections/04_fixed_point.tex}
        \input{sections/05_RAM_and_ROM.tex}
        \input{sections/06_serial_communications.tex}
        \input{sections/07_parallel_communications.tex}
        \input{sections/08_design_verification.tex}

        % DigDes content (reduced)
        \lstset{style=digdesvars} % adds digdes variable names to current style definition
        \part{DigDes}
        % \input{sections/DigDes/01_realisierungsformen}
        \input{sections/DigDes/02_digitaler_design_flow.tex}
        \input{sections/DigDes/03_hierarchie_und_konnektivitaet.tex}
        \input{sections/DigDes/04_nebenl_proc_und_proc_int.tex}
        \input{sections/DigDes/05_diskreter_ersatz_fuer_elektrische_signale.tex}
        \input{sections/DigDes/06_arithmetik.tex}
        \input{sections/DigDes/07_testbenches.tex}
        \input{sections/DigDes/08_modellparametrisierung.tex}
        % \input{sections/DigDes/99_appendix.tex}

    \end{layout}

    % QUALIS VHDL Quick Ref
    \includepdf[%
        pages={2},
        landscape=false,
        turn=false,
        pagecommand=\part{QUALIS QuickRef}
    ]{images/vhdl_Qualis_Quick_Reference_card_compact.pdf}

    % QUALIS 1164 Packages Quick Ref
    \includepdf[%
        pages={1},
        landscape=false,
        turn=false,
    ]{images/vhdl_Qualis_Quick_Reference_card_compact.pdf}
\end{document}