Note that these targets are bare-metal.

This is important to note, as it affects how easy it is to build a
binary, and that `#![no_std]` is mandatory.

A different PR should probably add this to all the other platform pages.

Author: thejpster

src/doc/rustc/src/platform-support/aarch64-unknown-none.md

@@ -1,6 +1,7 @@
 # `aarch64-unknown-none` and `aarch64-unknown-none-softfloat`
 
-**Tier: 2**
+* **Tier: 2**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 Bare-metal targets for CPUs in the Armv8-A architecture family, running in AArch64 mode.
 

src/doc/rustc/src/platform-support/armebv7r-none-eabi.md

@@ -1,6 +1,7 @@
 # `armebv7r-none-eabi` and `armebv7r-none-eabihf`
 
-**Tier: 2**
+* **Tier: 2**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 Bare-metal target for CPUs in the Armv7-R architecture family running in Big
 Endian mode. These processors support dual ARM/Thumb mode, with ARM mode as

src/doc/rustc/src/platform-support/armv4t-none-eabi.md

@@ -1,6 +1,7 @@
 # armv4t-none-eabi / thumbv4t-none-eabi
 
-Tier 3
+* **Tier:  3**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 These two targets are part of the [`arm-none-eabi`](arm-none-eabi.md) target
 group, and all the information there applies.

src/doc/rustc/src/platform-support/armv5te-none-eabi.md

@@ -1,6 +1,7 @@
 # `armv5te-none-eabi`
 
-**Tier: 3**
+* **Tier: 3**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 Bare-metal target for any cpu in the Armv5TE architecture family, supporting
 ARM/Thumb code interworking (aka `A32`/`T32`), with `A32` code as the default code

src/doc/rustc/src/platform-support/armv7a-none-eabi.md

@@ -1,7 +1,8 @@
 # `armv7a-none-eabi` and `armv7a-none-eabihf`
 
-**Tier: 2** for `armv7a-none-eabi`
-**Tier: 3** for `armv7a-none-eabihf`
+* **Tier: 2** for `armv7a-none-eabi`
+* **Tier: 3** for `armv7a-none-eabihf`
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 Bare-metal target for CPUs in the Armv7-A architecture family, supporting
 dual ARM/Thumb mode, with ARM mode as the default.

src/doc/rustc/src/platform-support/armv7r-none-eabi.md

@@ -1,6 +1,7 @@
 # `armv7r-none-eabi` and `armv7r-none-eabihf`
 
-**Tier: 2**
+* **Tier: 2**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 Bare-metal target for CPUs in the Armv7-R architecture family, supporting
 dual ARM/Thumb mode, with ARM mode as the default.

src/doc/rustc/src/platform-support/armv8r-none-eabihf.md

@@ -1,6 +1,7 @@
 # `armv8r-none-eabihf`
 
-**Tier: 3**
+* **Tier: 3**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 Bare-metal target for CPUs in the Armv8-R architecture family, supporting
 dual ARM/Thumb mode, with ARM mode as the default.

src/doc/rustc/src/platform-support/thumbv6m-none-eabi.md

@@ -1,6 +1,7 @@
 # `thumbv6m-none-eabi`
 
-**Tier: 2**
+* **Tier: 2**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 Bare-metal target for CPUs in the [Armv6-M] architecture family, supporting a
 subset of the [T32 ISA][t32-isa].

src/doc/rustc/src/platform-support/thumbv7em-none-eabi.md

@@ -1,6 +1,7 @@
 # `thumbv7em-none-eabi` and `thumbv7em-none-eabihf`
 
-**Tier: 2**
+* **Tier: 2**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 Bare-metal target for CPUs in the [Armv7E-M] architecture family, supporting a
 subset of the [T32 ISA][t32-isa].

src/doc/rustc/src/platform-support/thumbv7m-none-eabi.md

@@ -1,6 +1,7 @@
 # `thumbv7m-none-eabi`
 
-**Tier: 2**
+* **Tier: 2**
+* **Library Support:** core and alloc (bare-metal, `#![no_std]`)
 
 Bare-metal target for CPUs in the [Armv7-M] architecture family, supporting a
 subset of the [T32 ISA][t32-isa].