canio: mimxrt10xx: Fix Listener filters/masks initialization

Author: SamantazFox

ports/mimxrt10xx/common-hal/canio/CAN.c

@@ -267,7 +267,7 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, const mcu_pin_obj_t *
     config.enableLoopBack       = loopback;
     config.enableListenOnlyMode = silent;
     config.maxMbNum             = 64;
-    config.enableIndividMask    = true;
+    config.enableIndividMask    = true; // required to enable matching using a 'Listener'
     // config.disableSelfReception = true; // TODO: do we want to disable this?
 
     #if (defined(MIMXRT10XX_FLEXCAN_USE_IMPROVED_TIMING_CONFIG) && MIMXRT10XX_FLEXCAN_USE_IMPROVED_TIMING_CONFIG)
@@ -290,9 +290,6 @@ void common_hal_canio_can_construct(canio_can_obj_t *self, const mcu_pin_obj_t *
     FLEXCAN_TransferCreateHandle(self->data->base, &self->data->handle, mimxrt10xx_flexcan_callback, (void*)self);
 
     // Set rx mask to don't care on all bits.
-    FLEXCAN_SetRxMbGlobalMask(self->data->base, FLEXCAN_RX_MB_EXT_MASK(0x00, 0, 0));
-    FLEXCAN_SetRxFifoGlobalMask(self->data->base, FLEXCAN_RX_MB_EXT_MASK(0x00, 0, 0));
-
     flexcan_rx_fifo_config_t fifo_config;
     fifo_config.idFilterNum = 0;
     fifo_config.idFilterTable = self->data->rx_fifo_filter;

ports/mimxrt10xx/common-hal/canio/Listener.c

@@ -59,19 +59,39 @@ void common_hal_canio_listener_construct(canio_listener_obj_t *self, canio_can_o
 
     self->can = can;
 
-    for (size_t i = 0; i < nmatch; i++) {
-        if (matches[i]->extended) {
-            self->can->data->rx_fifo_filter[i] = FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(matches[i]->id, 0, 1);
-        } else {
-            self->can->data->rx_fifo_filter[i] = FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(matches[i]->id, 0, 0);
-        }
-    }
-
+    // Init configuration variables
     flexcan_rx_fifo_config_t fifo_config;
     fifo_config.idFilterNum = nmatch;
     fifo_config.idFilterTable = self->can->data->rx_fifo_filter;
     fifo_config.idFilterType = kFLEXCAN_RxFifoFilterTypeA;
     fifo_config.priority = kFLEXCAN_RxFifoPrioHigh;
+
+    if (nmatch == 0) {
+        // If the user has provided no matches, we need to set at least one
+        // filter that instructs the system to ignore all bits.
+        fifo_config.idFilterNum = 1;
+        self->can->data->rx_fifo_filter[0] = 0x0;
+        FLEXCAN_SetRxIndividualMask(self->can->data->base, 0, 0x0);
+    }
+    else {
+        // Required to touch any CAN registers
+        FLEXCAN_EnterFreezeMode(self->can->data->base);
+
+        for (size_t i = 0; i < nmatch; i++) {
+            if (matches[i]->extended) {
+                self->can->data->rx_fifo_filter[i] = FLEXCAN_RX_FIFO_EXT_FILTER_TYPE_A(matches[i]->id, 0, 1);
+                self->can->data->base->RXIMR[i] = FLEXCAN_RX_FIFO_EXT_MASK_TYPE_A(matches[i]->mask, 0, 1);
+            } else {
+                self->can->data->rx_fifo_filter[i] = FLEXCAN_RX_FIFO_STD_FILTER_TYPE_A(matches[i]->id, 0, 0);
+                self->can->data->base->RXIMR[i] = FLEXCAN_RX_FIFO_STD_MASK_TYPE_A(matches[i]->mask, 0, 0);
+            }
+        }
+
+        // For consistency, even though FLEXCAN_SetRxFifoConfig() below will
+        // enter and exit freeze mode again anyway
+        FLEXCAN_ExitFreezeMode(self->can->data->base);
+    }
+
     FLEXCAN_SetRxFifoConfig(self->can->data->base, &fifo_config, true);
 }
 

ports/mimxrt10xx/common-hal/canio/__init__.h

@@ -58,7 +58,12 @@ typedef uint32_t canio_can_filter_t;
 // Convert from frame array index to tx message buffer index.
 #define MIMXRT10XX_FLEXCAN_TX_ARRID_TO_MBID(x) (x + MIMXRT10XX_FLEXCAN_TX_MBID_MIN)
 
-// Limits the Canio module's Listener filter complexity.
+// We limit the amount of filter+mask pairs to 8 because above that the filters
+// are impacted by the global mask rather than individual masks alone, which is
+// not compatible with the current canio implementation.
+//
+// See Table 44-22 of the i.MX RT1060 Processor Reference Manual, Rev. 3
+// for more details.
 #define MIMXRT10XX_FLEXCAN_RX_FILTER_COUNT (8)
 
 // Enables/disables SDK calculated "improved" timing configuration.