arcv: Add support of nSIM simulator

Signed-off-by: Yuriy Kolerov <[email protected]>

Author: kolerov

Makefile.in

@@ -238,6 +238,25 @@ report-binutils: report-binutils-@default_target@
 report-gdb: report-gdb-@default_target@
 
 .PHONY: build-sim
+ifeq ($(SIM), nsim)
+# Using nsim simulator.
+ifeq (@default_target@, linux)
+$(error nSIM not supported)
+endif
+ifeq ($(shell command -v nsimdrv),)
+	$(error nsimdrv is not detected)
+endif
+DEJAGNU_SIM_LINK_FLAGS := \
+	-specs=semihost.specs -specs=arcv.specs \
+	-Wl,-defsym=txtmem_addr=0x0 -Wl,-defsym=datamem_addr=0x10000000 \
+	-Wl,-defsym=txtmem_len=32M -Wl,-defsym=datamem_len=32M
+DEJAGNU_SIM_LDSCRIPT := -Tarcv.ld
+SIM_PATH:=$(srcdir)/scripts/wrapper/nsim:$(srcdir)/scripts
+SIM_PREPARE:=PATH="$(SIM_PATH):$(INSTALL_DIR)/bin:$(PATH)" RISC_V_SYSROOT="$(SYSROOT)" \
+	DEJAGNU_SIM_LINK_FLAGS="$(DEJAGNU_SIM_LINK_FLAGS)"; export DEJAGNU_SIM_LINK_FLAGS; \
+	DEJAGNU_SIM_LDSCRIPT="$(DEJAGNU_SIM_LDSCRIPT)"; export DEJAGNU_SIM_LDSCRIPT;
+SIM_STAMP:=
+else
 ifeq ($(SIM),qemu)
 SIM_PATH:=$(srcdir)/scripts/wrapper/qemu:$(srcdir)/scripts
 SIM_PREPARE:=PATH="$(SIM_PATH):$(INSTALL_DIR)/bin:$(PATH)" RISC_V_SYSROOT="$(SYSROOT)"
@@ -260,7 +279,8 @@ ifeq ($(SIM),gdb)
 SIM_PATH:=$(INSTALL_DIR)/bin
 SIM_PREPARE:=
 else
-$(error "Only support SIM=spike, SIM=gdb or SIM=qemu (default).")
+$(error "Only support SIM=spike, SIM=gdb, SIM=nsim or SIM=qemu (default).")
+endif
 endif
 endif
 endif

scripts/march-to-cpu-opt

@@ -38,6 +38,45 @@ SPIKE_EXT_NOT_ALLOWED = [
   "zvl4096b",
 ]
 
+NSIM_EXT_ALLOWED = [
+    "i", "m", "a", "f", "d", "c", "e", "h", "v",
+    "zfh",
+    "zfhmin",
+    "zhinx",
+    "zhinxmin",
+    "zfinx",
+    "zdinx",
+    "zfa",
+    "zicsr",
+    "zifencei",
+    "zicond",
+    "zihintpause",
+    "zba",
+    "zbb",
+    "zbc",
+    "zbs",
+    "zca",
+    "zcb",
+    "zcf",
+    "zcd",
+    "zcmp",
+    "zcmt",
+    "zicbom",
+    "zicboz",
+    "zicbop",
+    "zvl32b",
+    "zvl64b",
+    "zvl128b",
+    "zvl256b",
+    "zvl512b",
+    "zvl1024b",
+    "zve32x",
+    "zve32f",
+    "zve64x",
+    "zve64f",
+    "zve64d"
+]
+
 CPU_OPTIONS = {
   "xlen":            "",
   "vlen":            "",
@@ -59,6 +98,8 @@ def parse_opt(argv):
     parser.add_argument('--print-spike-isa', action='store_true', default=False)
     parser.add_argument('--print-spike-varch', action='store_true',
                         default=False)
+    parser.add_argument('--print-nsim-family', action='store_true', default=False)
+    parser.add_argument('--print-nsim-isa', action='store_true', default=False)
     opt = parser.parse_args()
     return opt
 
@@ -203,6 +244,18 @@ def print_spike_varch():
 
     return "vlen:{0},elen:{1}".format(CPU_OPTIONS['vlen'], CPU_OPTIONS['elen'])
 
+def print_nsim_family():
+    return "rv{0}".format(CPU_OPTIONS['xlen'])
+
+def print_nsim_isa():
+    cpu_options = ["-all"]
+
+    for ext in CPU_OPTIONS['extensions']:
+        if ext in NSIM_EXT_ALLOWED:
+            cpu_options.append(ext)
+
+    return ".".join(cpu_options)
+
 class TestArchStringParse(unittest.TestCase):
     def _test(self, arch, expected_arch_list, expected_vlen=0):
          exts = parse_march(arch)
@@ -301,5 +354,11 @@ def main(argv):
     if opt.print_spike_varch:
         print(print_spike_varch())
 
+    if opt.print_nsim_family:
+        print(print_nsim_family())
+
+    if opt.print_nsim_isa:
+        print(print_nsim_isa())
+
 if __name__ == '__main__':
     sys.exit(main(sys.argv))

scripts/wrapper/nsim/riscv32-snps-elf-run

@@ -0,0 +1 @@
+riscv32-unknown-elf-run

scripts/wrapper/nsim/riscv32-unknown-elf-run

@@ -0,0 +1,11 @@
+#!/bin/bash
+
+family="$(march-to-cpu-opt --elf-file-path $1 --print-nsim-family)"
+isa="$(march-to-cpu-opt --elf-file-path $1 --print-nsim-isa)"
+
+nsimdrv \
+    -p nsim_isa_family=${family} \
+    -p nsim_isa_ext=${isa} \
+    -p nsim_semihosting=1 \
+    -p enable_exceptions=0 \
+    "$@"

scripts/wrapper/nsim/riscv64-snps-elf-run

@@ -0,0 +1 @@
+riscv32-unknown-elf-run

scripts/wrapper/nsim/riscv64-unknown-elf-run

@@ -0,0 +1 @@
+riscv32-unknown-elf-run