|
| 1 | +From a5fa3b17cb10ce020f8b7fe6a26c45d75f55b481 Mon Sep 17 00:00:00 2001 |
| 2 | +From: Alexey Brodkin < [email protected]> |
| 3 | +Date: Fri, 31 Mar 2017 11:14:35 +0300 |
| 4 | +Subject: [PATCH 2/2] axs103: Support slave core kick-start on axs103 v1.1 |
| 5 | + firmware |
| 6 | + |
| 7 | +In axs103 v1.1 procedure to kick-start slave cores has changed quite a bit |
| 8 | +compared t previous implementation. |
| 9 | + |
| 10 | +In particular: |
| 11 | + * We used to have a generic START bit for all cores selected by CORE_SEL |
| 12 | + mask. But now we don't touch CORE_SEL at all because we have a dedicated |
| 13 | + START bit for each core: |
| 14 | + bit 0: Core 0 (master) |
| 15 | + bit 1: Core 1 (slave) |
| 16 | + * Now there's no need to select "manual" mode of core start |
| 17 | + |
| 18 | +Additional challenge for us is how to tell which axs103 firmware we're |
| 19 | +dealing with. For now we'll rely on ARC core version which was bumped |
| 20 | +from 2.1c to 3.0. |
| 21 | + |
| 22 | +Signed-off-by: Alexey Brodkin < [email protected]> |
| 23 | +--- |
| 24 | + board/synopsys/axs10x/axs10x.c | 23 +++++++++++++++++++++-- |
| 25 | + 1 file changed, 21 insertions(+), 2 deletions(-) |
| 26 | + |
| 27 | +diff --git a/board/synopsys/axs10x/axs10x.c b/board/synopsys/axs10x/axs10x.c |
| 28 | +index 57c790220f71..e6b69da3da7f 100644 |
| 29 | +--- a/board/synopsys/axs10x/axs10x.c |
| 30 | ++++ b/board/synopsys/axs10x/axs10x.c |
| 31 | +@@ -7,6 +7,7 @@ |
| 32 | + #include <common.h> |
| 33 | + #include <dwmmc.h> |
| 34 | + #include <malloc.h> |
| 35 | ++#include <asm/arcregs.h> |
| 36 | + #include "axs10x.h" |
| 37 | + |
| 38 | + DECLARE_GLOBAL_DATA_PTR; |
| 39 | +@@ -66,9 +67,27 @@ void smp_kick_all_cpus(void) |
| 40 | + #define BITS_START_MODE 4 |
| 41 | + #define BITS_CORE_SEL 9 |
| 42 | + |
| 43 | ++/* |
| 44 | ++ * In axs103 v1.1 START bits semantics has changed quite a bit. |
| 45 | ++ * We used to have a generic START bit for all cores selected by CORE_SEL mask. |
| 46 | ++ * But now we don't touch CORE_SEL at all because we have a dedicated START bit |
| 47 | ++ * for each core: |
| 48 | ++ * bit 0: Core 0 (master) |
| 49 | ++ * bit 1: Core 1 (slave) |
| 50 | ++ */ |
| 51 | ++#define BITS_START_CORE1 1 |
| 52 | ++ |
| 53 | ++#define ARCVER_HS38_3_0 0x53 |
| 54 | ++ |
| 55 | ++ int core_family = read_aux_reg(ARC_AUX_IDENTITY) & 0xff; |
| 56 | + int cmd = readl((void __iomem *)AXC003_CREG_CPU_START); |
| 57 | +- cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START); |
| 58 | +- cmd &= ~(1 << BITS_START_MODE); |
| 59 | ++ |
| 60 | ++ if (core_family < ARCVER_HS38_3_0) { |
| 61 | ++ cmd |= (1 << BITS_CORE_SEL) | (1 << BITS_START); |
| 62 | ++ cmd &= ~(1 << BITS_START_MODE); |
| 63 | ++ } else { |
| 64 | ++ cmd |= (1 << BITS_START_CORE1); |
| 65 | ++ } |
| 66 | + writel(cmd, (void __iomem *)AXC003_CREG_CPU_START); |
| 67 | + } |
| 68 | + #endif |
| 69 | +-- |
| 70 | +2.7.4 |
| 71 | + |
0 commit comments