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arc: axs10x - bump Linux kernel & headers to 4.2 release
Linux kernel 4.2 was finally released, so bumping from 4.2-rc5 to final release. Updating Linux headers to 4.2 branch since they are introduced in Buildroot as well already. Also adding 1 back-ported patch that makes SD/MMC cards usable on AXS boards. This patch will be a part of 4.3 (already in linux-next) and hopefully will make its way in 4.2.1. Once that patch appears in 4.2.x it must be removed from here. Cc: Peter Korsgaard <[email protected]> Cc: Thomas Petazzoni <[email protected]> Signed-off-by: Alexey Brodkin <[email protected]>
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‎board/synopsys/axs10x/patches/linux/0001-mmc-dw_mmc-handle-data-blocks-than-4kB-if-IDMAC-is-u.patch‎

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From 969872e334937bd0956887a925f20f7a446af5f6 Mon Sep 17 00:00:00 2001
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From: Alexey Brodkin <[email protected]>
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Date: Thu, 25 Jun 2015 11:25:07 +0300
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Subject: [PATCH] mmc: dw_mmc: handle data blocks > than 4kB if IDMAC is used
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As per DW MobileStorage databook "each descriptor can transfer up to 4kB
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of data in chained mode", moreover buffer size that is put in "des1" is
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limited to 13 bits, i.e. for example on attempt to
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IDMAC_SET_BUFFER1_SIZE(desc, 8192) size value that's effectively written
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will be 0.
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On the platform with 8kB PAGE_SIZE I see dw_mmc gets data blocks in
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SG-list of 8kB size and that leads to unpredictable behavior of the
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SD/MMC controller.
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In particular on write to FAT partition of SD-card the controller will
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stuck in the middle of DMA transaction.
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Solution to the problem is simple - we need to pass large (> 4kB) data
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buffers to the controller via multiple descriptors. And that's what
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that change does.
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What's interesting I did try original driver on same platform but
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configured with 4kB PAGE_SIZE and may confirm that data blocks passed
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in SG-list to dw_mmc never exeed 4kB limit - that explains why nobody
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ever faced a problem I did.
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Signed-off-by: Alexey Brodkin <[email protected]>
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Cc: Seungwon Jeon <[email protected]>
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Cc: Jaehoon Chung <[email protected]>
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Cc: Ulf Hansson <[email protected]>
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Cc: [email protected]
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Cc: [email protected]
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Signed-off-by: Jaehoon Chung <[email protected]>
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---
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drivers/mmc/host/dw_mmc.c | 109 ++++++++++++++++++++++++++++++----------------
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1 file changed, 71 insertions(+), 38 deletions(-)
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diff --git a/drivers/mmc/host/dw_mmc.c b/drivers/mmc/host/dw_mmc.c
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index 40e9d8e..e41fb74 100644
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--- a/drivers/mmc/host/dw_mmc.c
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+++ b/drivers/mmc/host/dw_mmc.c
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@@ -99,6 +99,9 @@ struct idmac_desc {
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__le32 des3; /* buffer 2 physical address */
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};
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+
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+/* Each descriptor can transfer up to 4KB of data in chained mode */
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+#define DW_MCI_DESC_DATA_LENGTH 0x1000
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#endif /* CONFIG_MMC_DW_IDMAC */
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static bool dw_mci_reset(struct dw_mci *host);
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@@ -462,66 +465,96 @@ static void dw_mci_idmac_complete_dma(struct dw_mci *host)
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static void dw_mci_translate_sglist(struct dw_mci *host, struct mmc_data *data,
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unsigned int sg_len)
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{
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+ unsigned int desc_len;
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int i;
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if (host->dma_64bit_address == 1) {
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- struct idmac_desc_64addr *desc = host->sg_cpu;
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+ struct idmac_desc_64addr *desc_first, *desc_last, *desc;
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+
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+ desc_first = desc_last = desc = host->sg_cpu;
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- for (i = 0; i < sg_len; i++, desc++) {
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+ for (i = 0; i < sg_len; i++) {
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unsigned int length = sg_dma_len(&data->sg[i]);
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u64 mem_addr = sg_dma_address(&data->sg[i]);
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- /*
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- * Set the OWN bit and disable interrupts for this
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- * descriptor
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- */
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- desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
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- IDMAC_DES0_CH;
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- /* Buffer length */
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- IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, length);
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-
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- /* Physical address to DMA to/from */
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- desc->des4 = mem_addr & 0xffffffff;
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- desc->des5 = mem_addr >> 32;
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+ for ( ; length ; desc++) {
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+ desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
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+ length : DW_MCI_DESC_DATA_LENGTH;
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+
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+ length -= desc_len;
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+
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+ /*
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+ * Set the OWN bit and disable interrupts
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+ * for this descriptor
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+ */
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+ desc->des0 = IDMAC_DES0_OWN | IDMAC_DES0_DIC |
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+ IDMAC_DES0_CH;
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+
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+ /* Buffer length */
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+ IDMAC_64ADDR_SET_BUFFER1_SIZE(desc, desc_len);
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+
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+ /* Physical address to DMA to/from */
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+ desc->des4 = mem_addr & 0xffffffff;
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+ desc->des5 = mem_addr >> 32;
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+
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+ /* Update physical address for the next desc */
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+ mem_addr += desc_len;
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+
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+ /* Save pointer to the last descriptor */
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+ desc_last = desc;
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+ }
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}
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/* Set first descriptor */
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- desc = host->sg_cpu;
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- desc->des0 |= IDMAC_DES0_FD;
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+ desc_first->des0 |= IDMAC_DES0_FD;
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/* Set last descriptor */
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- desc = host->sg_cpu + (i - 1) *
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- sizeof(struct idmac_desc_64addr);
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- desc->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
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- desc->des0 |= IDMAC_DES0_LD;
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+ desc_last->des0 &= ~(IDMAC_DES0_CH | IDMAC_DES0_DIC);
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+ desc_last->des0 |= IDMAC_DES0_LD;
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} else {
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- struct idmac_desc *desc = host->sg_cpu;
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+ struct idmac_desc *desc_first, *desc_last, *desc;
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+
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+ desc_first = desc_last = desc = host->sg_cpu;
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- for (i = 0; i < sg_len; i++, desc++) {
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+ for (i = 0; i < sg_len; i++) {
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unsigned int length = sg_dma_len(&data->sg[i]);
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u32 mem_addr = sg_dma_address(&data->sg[i]);
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- /*
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- * Set the OWN bit and disable interrupts for this
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- * descriptor
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- */
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- desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
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- IDMAC_DES0_DIC | IDMAC_DES0_CH);
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- /* Buffer length */
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- IDMAC_SET_BUFFER1_SIZE(desc, length);
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+ for ( ; length ; desc++) {
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+ desc_len = (length <= DW_MCI_DESC_DATA_LENGTH) ?
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+ length : DW_MCI_DESC_DATA_LENGTH;
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+
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+ length -= desc_len;
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+
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+ /*
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+ * Set the OWN bit and disable interrupts
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+ * for this descriptor
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+ */
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+ desc->des0 = cpu_to_le32(IDMAC_DES0_OWN |
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+ IDMAC_DES0_DIC |
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+ IDMAC_DES0_CH);
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+
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+ /* Buffer length */
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+ IDMAC_SET_BUFFER1_SIZE(desc, desc_len);
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- /* Physical address to DMA to/from */
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- desc->des2 = cpu_to_le32(mem_addr);
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+ /* Physical address to DMA to/from */
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+ desc->des2 = cpu_to_le32(mem_addr);
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+
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+ /* Update physical address for the next desc */
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+ mem_addr += desc_len;
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+
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+ /* Save pointer to the last descriptor */
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+ desc_last = desc;
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+ }
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}
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/* Set first descriptor */
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- desc = host->sg_cpu;
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- desc->des0 |= cpu_to_le32(IDMAC_DES0_FD);
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+ desc_first->des0 |= cpu_to_le32(IDMAC_DES0_FD);
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/* Set last descriptor */
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- desc = host->sg_cpu + (i - 1) * sizeof(struct idmac_desc);
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- desc->des0 &= cpu_to_le32(~(IDMAC_DES0_CH | IDMAC_DES0_DIC));
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- desc->des0 |= cpu_to_le32(IDMAC_DES0_LD);
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+ desc_last->des0 &= cpu_to_le32(~(IDMAC_DES0_CH |
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+ IDMAC_DES0_DIC));
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+ desc_last->des0 |= cpu_to_le32(IDMAC_DES0_LD);
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}
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wmb();
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@@ -2394,7 +2427,7 @@ static int dw_mci_init_slot(struct dw_mci *host, unsigned int id)
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#ifdef CONFIG_MMC_DW_IDMAC
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mmc->max_segs = host->ring_size;
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mmc->max_blk_size = 65536;
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- mmc->max_seg_size = 0x1000;
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+ mmc->max_seg_size = DW_MCI_DESC_DATA_LENGTH;
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mmc->max_req_size = mmc->max_seg_size * host->ring_size;
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mmc->max_blk_count = mmc->max_req_size / 512;
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#else
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--
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2.4.3
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‎configs/snps_axs101_defconfig‎

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@@ -10,13 +10,14 @@ BR2_ROOTFS_OVERLAY="board/synopsys/axs10x/fs-overlay"
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# Headers
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BR2_KERNEL_HEADERS_VERSION=y
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BR2_DEFAULT_KERNEL_VERSION="4.1"
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BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_1=y
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BR2_DEFAULT_KERNEL_VERSION="4.2"
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BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_2=y
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# Kernel
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BR2_LINUX_KERNEL=y
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BR2_LINUX_KERNEL_CUSTOM_VERSION=y
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BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.2-rc5"
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BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.2"
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BR2_LINUX_KERNEL_PATCH="board/synopsys/axs10x/patches/linux"
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BR2_LINUX_KERNEL_DEFCONFIG="axs101"
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# Bootloader

‎configs/snps_axs103_defconfig‎

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@@ -11,13 +11,14 @@ BR2_ROOTFS_OVERLAY="board/synopsys/axs10x/fs-overlay"
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# Headers
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BR2_KERNEL_HEADERS_VERSION=y
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BR2_DEFAULT_KERNEL_VERSION="4.1"
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BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_1=y
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BR2_DEFAULT_KERNEL_VERSION="4.2"
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BR2_PACKAGE_HOST_LINUX_HEADERS_CUSTOM_4_2=y
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# Kernel
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BR2_LINUX_KERNEL=y
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BR2_LINUX_KERNEL_CUSTOM_VERSION=y
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BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.2-rc5"
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BR2_LINUX_KERNEL_CUSTOM_VERSION_VALUE="4.2"
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BR2_LINUX_KERNEL_PATCH="board/synopsys/axs10x/patches/linux"
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BR2_LINUX_KERNEL_DEFCONFIG="axs103_smp"
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# Bootloader

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