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Add GCC patches for HS48 processors
Signed-off-by: Evgeniy Didin <[email protected]>
1 parent 1a3164b commit aec230e

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‎package/gcc/arc-2019.03-rc1/0001-ARC-PR-88409-miscompilation-due-to-missing-cc-clobbe.patch‎

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From 274a5a1d63fc5e4ea942165702363547e71525ac Mon Sep 17 00:00:00 2001
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From: Vineet Gupta <[email protected]>
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Date: Fri, 29 Mar 2019 17:45:20 +0200
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Subject: [PATCH 1/7] [ARC] PR 88409: miscompilation due to missing cc clobber
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in longlong.h macros
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simple test such as below was failing.
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| void main(int argc, char *argv[])
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| {
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| size_t total_time = 115424; // expected 115.424
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| double secs = (double)total_time/(double)1000;
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| printf("%s %d %lf\n", "secs", total_time, secs); // prints 113.504
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| printf("%d\n", (size_t)secs);
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| }
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The printf eventually called into glibc stdlib/divrem.c:__mpn_divrem()
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which uses the __arc__ specific inline asm macros from longlong.h which
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were causing miscompilation.
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include/
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2019-03-28 Vineet Gupta <[email protected]>
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PR 89877
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* longlong.h [__arc__] (add_ssaaaa): Add cc clobber
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(sub_ddmmss): Likewise.
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Signed-off-by: Claudiu Zissulescu <[email protected]>
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---
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include/longlong.h | 6 ++++--
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1 file changed, 4 insertions(+), 2 deletions(-)
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diff --git a/include/longlong.h b/include/longlong.h
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index 7f3dc17dc0a..8771365b9dc 100644
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--- a/include/longlong.h
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+++ b/include/longlong.h
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@@ -199,7 +199,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
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: "%r" ((USItype) (ah)), \
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"rICal" ((USItype) (bh)), \
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"%r" ((USItype) (al)), \
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- "rICal" ((USItype) (bl)))
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+ "rICal" ((USItype) (bl)) \
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+ : "cc")
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#define sub_ddmmss(sh, sl, ah, al, bh, bl) \
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__asm__ ("sub.f %1, %4, %5\n\tsbc %0, %2, %3" \
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: "=r" ((USItype) (sh)), \
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@@ -207,7 +208,8 @@ extern UDItype __udiv_qrnnd (UDItype *, UDItype, UDItype, UDItype);
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: "r" ((USItype) (ah)), \
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"rICal" ((USItype) (bh)), \
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"r" ((USItype) (al)), \
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- "rICal" ((USItype) (bl)))
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+ "rICal" ((USItype) (bl)) \
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+ : "cc")
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#define __umulsidi3(u,v) ((UDItype)(USItype)u*(USItype)v)
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#ifdef __ARC_NORM__
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--
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2.16.2
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‎package/gcc/arc-2019.03-rc1/0002-ARC-Fix-for-PR89838.patch‎

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From 4c33b1cb6400341121700473da03d4083990a093 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <[email protected]>
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Date: Mon, 1 Apr 2019 13:03:55 +0300
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Subject: [PATCH 2/7] [ARC] Fix for PR89838.
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gcc/
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xxxx-xx-xx Claudiu Zissulescu <[email protected]>
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* config/arc/arc.c (arc_legitimize_pic_address): Emit an move
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instruction if needed.
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(prepare_pic_move): Always provide an spare register.
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/gcc/testsuite
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xxxx-xx-xx Claudiu Zissulescu <[email protected]>
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* gcc.target/arc/pr89838.c: New file.
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---
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gcc/config/arc/arc.c | 9 ++++++++-
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gcc/testsuite/gcc.target/arc/pr89838.c | 16 ++++++++++++++++
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2 files changed, 24 insertions(+), 1 deletion(-)
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create mode 100644 gcc/testsuite/gcc.target/arc/pr89838.c
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diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
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index ba2e3dd8208..83664d4d64f 100644
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--- a/gcc/config/arc/arc.c
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+++ b/gcc/config/arc/arc.c
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@@ -6093,6 +6093,13 @@ arc_legitimize_pic_address (rtx orig, rtx oldx)
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if (base == op0 && pat == op1)
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return orig;
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+ if (GET_CODE (base) == PLUS)
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+ {
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+ gcc_assert (oldx != NULL_RTX);
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+ gcc_assert (REG_P (oldx));
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+ emit_insn (gen_rtx_SET (oldx, base));
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+ base = oldx;
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+ }
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if (GET_CODE (pat) == CONST_INT)
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pat = plus_constant (Pmode, base, INTVAL (pat));
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else
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@@ -6285,7 +6292,7 @@ prepare_pic_move (rtx *operands, machine_mode)
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else
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{
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rtx temp = (reload_in_progress ? operands[0]
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- : flag_pic? gen_reg_rtx (Pmode) : NULL_RTX);
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+ : gen_reg_rtx (Pmode));
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operands[1] = arc_legitimize_pic_address (operands[1], temp);
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}
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}
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diff --git a/gcc/testsuite/gcc.target/arc/pr89838.c b/gcc/testsuite/gcc.target/arc/pr89838.c
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new file mode 100644
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index 00000000000..559434ac87e
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--- /dev/null
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+++ b/gcc/testsuite/gcc.target/arc/pr89838.c
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@@ -0,0 +1,16 @@
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+/* { dg-do compile } */
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+/* { dg-require-effective-target tls } */
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+/* { dg-options "-O2" } */
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+
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+extern void foo (void);
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+extern void bar (void *);
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+
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+struct {
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+ int __attribute__(()) a;
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+ int __attribute__(()) b;
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+} __thread c __attribute__((tls_model("initial-exec")));
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+
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+void foo (void)
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+{
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+ bar (&c.b);
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+}
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--
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2.16.2
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‎package/gcc/arc-2019.03-rc1/0003-ARC-Cleanup-TUNE-variants.patch‎

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From 62f2c9d66765c2dbfc0ec895e1242f36bac63cf3 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <[email protected]>
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Date: Tue, 2 Apr 2019 15:28:41 +0300
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Subject: [PATCH 3/7] [ARC] Cleanup TUNE variants
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Cleanup TUNE variants.
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gcc/
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xxxx-xx-xx Claudiu Zissulescu <[email protected]>
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* config/arc/arc.c (arc_sched_issue_rate): Use correct enum.
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* config/arc/arc.md (tune): Update tune attribute, and use correct
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enums.
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(tune_dspmpy): Likewise.
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---
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gcc/config/arc/arc.c | 4 ++--
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gcc/config/arc/arc.md | 22 ++++++++++------------
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2 files changed, 12 insertions(+), 14 deletions(-)
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diff --git a/gcc/config/arc/arc.c b/gcc/config/arc/arc.c
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index 83664d4d64f..b428bfbed63 100644
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--- a/gcc/config/arc/arc.c
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+++ b/gcc/config/arc/arc.c
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@@ -490,8 +490,8 @@ arc_sched_issue_rate (void)
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{
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switch (arc_tune)
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{
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- case TUNE_ARCHS4X:
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- case TUNE_ARCHS4XD:
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+ case ARC_TUNE_ARCHS4X:
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+ case ARC_TUNE_ARCHS4XD:
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return 3;
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default:
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break;
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diff --git a/gcc/config/arc/arc.md b/gcc/config/arc/arc.md
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index 241506ea785..42a24e16ff4 100644
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--- a/gcc/config/arc/arc.md
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+++ b/gcc/config/arc/arc.md
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@@ -621,22 +621,20 @@
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;; is made that makes conditional execution required.
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(define_attr "tune" "none,arc600,arc7xx,arc700_4_2_std,arc700_4_2_xmac, \
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-core_3, archs4x, archs4xd, archs4xd_slow"
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+archs4x, archs4xd"
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(const
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- (cond [(symbol_ref "arc_tune == TUNE_ARC600")
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+ (cond [(symbol_ref "arc_tune == ARC_TUNE_ARC600")
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(const_string "arc600")
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(symbol_ref "arc_tune == ARC_TUNE_ARC7XX")
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(const_string "arc7xx")
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- (symbol_ref "arc_tune == TUNE_ARC700_4_2_STD")
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+ (symbol_ref "arc_tune == ARC_TUNE_ARC700_4_2_STD")
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(const_string "arc700_4_2_std")
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- (symbol_ref "arc_tune == TUNE_ARC700_4_2_XMAC")
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+ (symbol_ref "arc_tune == ARC_TUNE_ARC700_4_2_XMAC")
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(const_string "arc700_4_2_xmac")
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- (symbol_ref "arc_tune == ARC_TUNE_CORE_3")
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- (const_string "core_3")
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- (symbol_ref "arc_tune == TUNE_ARCHS4X")
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+ (symbol_ref "arc_tune == ARC_TUNE_ARCHS4X")
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(const_string "archs4x")
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- (ior (symbol_ref "arc_tune == TUNE_ARCHS4XD")
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- (symbol_ref "arc_tune == TUNE_ARCHS4XD_SLOW"))
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+ (ior (symbol_ref "arc_tune == ARC_TUNE_ARCHS4XD")
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+ (symbol_ref "arc_tune == ARC_TUNE_ARCHS4XD_SLOW"))
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(const_string "archs4xd")]
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(const_string "none"))))
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@@ -647,10 +645,10 @@ core_3, archs4x, archs4xd, archs4xd_slow"
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(define_attr "tune_dspmpy" "none, slow, fast"
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(const
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- (cond [(ior (symbol_ref "arc_tune == TUNE_ARCHS4X")
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- (symbol_ref "arc_tune == TUNE_ARCHS4XD"))
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+ (cond [(ior (symbol_ref "arc_tune == ARC_TUNE_ARCHS4X")
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+ (symbol_ref "arc_tune == ARC_TUNE_ARCHS4XD"))
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(const_string "fast")
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- (symbol_ref "arc_tune == TUNE_ARCHS4XD_SLOW")
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+ (symbol_ref "arc_tune == ARC_TUNE_ARCHS4XD_SLOW")
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(const_string "slow")]
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(const_string "none"))))
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--
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2.16.2
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‎package/gcc/arc-2019.03-rc1/0004-FIX-MNL-Don-t-throw-errors-when-compiling-for-xarch.patch‎

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From ad177abf331128501b92e946e532ac0361321628 Mon Sep 17 00:00:00 2001
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From: Claudiu Zissulescu <[email protected]>
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Date: Tue, 2 Apr 2019 16:43:15 +0300
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Subject: [PATCH 4/7] [FIX][MNL] Don't throw errors when compiling for xarch
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---
7+
gcc/gimple-ssa-store-merging.c | 4 ++++
8+
1 file changed, 4 insertions(+)
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diff --git a/gcc/gimple-ssa-store-merging.c b/gcc/gimple-ssa-store-merging.c
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index 9002bfbbad0..dbcd78ed90a 100644
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--- a/gcc/gimple-ssa-store-merging.c
13+
+++ b/gcc/gimple-ssa-store-merging.c
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@@ -161,7 +161,11 @@
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#include "selftest.h"
16+
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/* The maximum size (in bits) of the stores this pass should generate. */
18+
+#ifdef TARGET_LL64
19+
#define MAX_STORE_BITSIZE (TARGET_LL64 ? 2 * BITS_PER_WORD : BITS_PER_WORD)
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+#else
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+#define MAX_STORE_BITSIZE (BITS_PER_WORD)
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+#endif
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#define MAX_STORE_BYTES (MAX_STORE_BITSIZE / BITS_PER_UNIT)
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/* Limit to bound the number of aliasing checks for loads with the same
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--
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2.16.2
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