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| 1 | +From a2afd96610c0b0ae5b50cb2761fbba87a7a3765c Mon Sep 17 00:00:00 2001 |
| 2 | +From: Lada Trimasova < [email protected]> |
| 3 | +Date: Thu, 28 Apr 2016 18:09:55 +0300 |
| 4 | +Subject: [PATCH] Use frequency config in pre-bootloader |
| 5 | + |
| 6 | +In this release we get rid of hack when frequency depends on cores number. |
| 7 | +Now use frequency config in pre-bootloader. |
| 8 | + |
| 9 | +Signed-off-by: Lada Trimasova < [email protected]> |
| 10 | +--- |
| 11 | + arch/arc/plat-axs10x/axs10x.c | 44 ++----------------------------------------- |
| 12 | + 1 file changed, 2 insertions(+), 42 deletions(-) |
| 13 | + |
| 14 | +diff --git a/arch/arc/plat-axs10x/axs10x.c b/arch/arc/plat-axs10x/axs10x.c |
| 15 | +index 1b0f0f4..3fb3de1 100644 |
| 16 | +--- a/arch/arc/plat-axs10x/axs10x.c |
| 17 | ++++ b/arch/arc/plat-axs10x/axs10x.c |
| 18 | +@@ -390,50 +390,10 @@ axs103_set_freq(unsigned int id, unsigned int fd, unsigned int od) |
| 19 | + static void __init axs103_early_init(void) |
| 20 | + { |
| 21 | + /* |
| 22 | +- * AXS103 configurations for SMP/QUAD configurations share device tree |
| 23 | +- * which defaults to 90 MHz. However recent failures of Quad config |
| 24 | +- * revealed P&R timing violations so clamp it down to safe 50 MHz |
| 25 | +- * Instead of duplicating defconfig/DT for SMP/QUAD, add a small hack |
| 26 | +- * |
| 27 | +- * This hack is really hacky as of now. Fix it properly by getting the |
| 28 | +- * number of cores as return value of platform's early SMP callback |
| 29 | ++ * In this release we use frequency config in pre-bootloader. |
| 30 | + */ |
| 31 | +-#ifdef CONFIG_ARC_MCIP |
| 32 | +- unsigned int num_cores = (read_aux_reg(ARC_REG_MCIP_BCR) >> 16) & 0x3F; |
| 33 | +- if (num_cores > 2) |
| 34 | +- arc_set_core_freq(50 * 1000000); |
| 35 | +- else if (num_cores == 2) |
| 36 | +- arc_set_core_freq(75 * 1000000); |
| 37 | +-#endif |
| 38 | + |
| 39 | +- switch (arc_get_core_freq()/1000000) { |
| 40 | +- case 33: |
| 41 | +- axs103_set_freq(1, 1, 1); |
| 42 | +- break; |
| 43 | +- case 50: |
| 44 | +- axs103_set_freq(1, 30, 20); |
| 45 | +- break; |
| 46 | +- case 75: |
| 47 | +- axs103_set_freq(2, 45, 10); |
| 48 | +- break; |
| 49 | +- case 90: |
| 50 | +- axs103_set_freq(2, 54, 10); |
| 51 | +- break; |
| 52 | +- case 100: |
| 53 | +- axs103_set_freq(1, 30, 10); |
| 54 | +- break; |
| 55 | +- case 125: |
| 56 | +- axs103_set_freq(2, 45, 6); |
| 57 | +- break; |
| 58 | +- default: |
| 59 | +- /* |
| 60 | +- * In this case, core_frequency derived from |
| 61 | +- * DT "clock-frequency" might not match with board value. |
| 62 | +- * Hence update it to match the board value. |
| 63 | +- */ |
| 64 | +- arc_set_core_freq(axs103_get_freq() * 1000000); |
| 65 | +- break; |
| 66 | +- } |
| 67 | ++ arc_set_core_freq(axs103_get_freq() * 1000000); |
| 68 | + |
| 69 | + pr_info("Freq is %dMHz\n", axs103_get_freq()); |
| 70 | + |
| 71 | +-- |
| 72 | +2.5.0 |
| 73 | + |
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