|
| 1 | + |
| 2 | +/*************************************************************************/ |
| 3 | +/*************************************************************************/ |
| 4 | +/** **/ |
| 5 | +/** Copyright (C) 1989-2016 Synopsys, Inc. **/ |
| 6 | +/** All Rights Reserved. **/ |
| 7 | +/** **/ |
| 8 | +/** SYNOPSYS CONFIDENTIAL **/ |
| 9 | +/** **/ |
| 10 | +/** This is an unpublished proprietary work of Synopsys, Inc., and is **/ |
| 11 | +/** fully protected under copyright and trade secret laws. You may not **/ |
| 12 | +/** view, use, disclose, copy, or distribute this file or any **/ |
| 13 | +/** information contained herein except pursuant to a valid written **/ |
| 14 | +/** license from Synopsys. **/ |
| 15 | +/** **/ |
| 16 | +/** For more information, contact **/ |
| 17 | +/** [email protected] or call (650) 584-1631 **/ |
| 18 | +/** **/ |
| 19 | +/*************************************************************************/ |
| 20 | +/*************************************************************************/ |
| 21 | +#ifndef __BOARD_EMSDP_H__ |
| 22 | +#define __BOARD_EMSDP_H__ |
| 23 | + |
| 24 | + |
| 25 | +/** |
| 26 | + * Clock |
| 27 | + */ |
| 28 | +#define EMSDP_REF_CLOCK (100000000) |
| 29 | + |
| 30 | +#define EMSDP_UART_REF_CLOCK (100000000) |
| 31 | +#define EMSDP_AUDIO_REF_CLOCK (24576000) |
| 32 | + |
| 33 | +#if (defined(FAST_UART) ) |
| 34 | + #define EMSDP_UART_BAUDRATE (6250000) |
| 35 | +#else |
| 36 | + #define EMSDP_UART_BAUDRATE (115200) |
| 37 | +#endif |
| 38 | + |
| 39 | +#define EMSDP_I2C_CLOCK (EMSDP_REF_CLOCK) |
| 40 | + |
| 41 | +//APB Peripheral address map |
| 42 | +#define EMSDP_CRU_BASE (0xF0000000U) |
| 43 | +#define EMSDP_CREG_BASE (0xF0001000U) |
| 44 | +#define EMSDP_GPIO_BASE (0xF0002000U) |
| 45 | +#define EMSDP_TRNG_BASE (0xF0003000U) |
| 46 | +#define EMSDP_DBG_UART_BASE (0xF0004000U) |
| 47 | +#define EMSDP_WDT_BASE (0xF0005000U) |
| 48 | +#define EMSDP_TIMERS0_BASE (0xF0006000U) |
| 49 | +#define EMSDP_TIMERS1_BASE (0xF0007000U) |
| 50 | +#define EMSDP_SPI_BASE (0xF0008000U) |
| 51 | +#define EMSDP_UART_BASE (0xF0009000U) |
| 52 | +#define EMSDP_SDIO_BASE (0xF0010000U) |
| 53 | +#define EMSDP_FLASH_BASE (0xF1000000U) |
| 54 | +#define EMSDP_EBI_BASE (0xF2000000U) |
| 55 | +#define EMSDP_PSRAM_BASE (0xF2001000U) |
| 56 | + |
| 57 | + |
| 58 | +/** |
| 59 | +* Mapping of printf information |
| 60 | +*/ |
| 61 | + #define DBG_init dbg_init |
| 62 | + #define DBG_print dbg_printf |
| 63 | + #define DBG_getChar(x) \ |
| 64 | + { \ |
| 65 | + DW_UART_STRUCT_PTR uart = (DW_UART_STRUCT_PTR) (DBG_PORT); \ |
| 66 | + x = dw_uart_getChar(uart); \ |
| 67 | + } |
| 68 | + #define DBG_finish() |
| 69 | + #define DBG_finish_with_error() |
| 70 | + #define DBG_install(x) \ |
| 71 | + { \ |
| 72 | + DW_UART_STRUCT_PTR uart = (DW_UART_STRUCT_PTR) (DBG_PORT); \ |
| 73 | + uart->IER.DATA32 = DW_UART_IER_DATA_AVAIL; \ |
| 74 | + board_installHandler(x, DBG_ISR); \ |
| 75 | + } |
| 76 | + |
| 77 | + |
| 78 | +//ARC Exceptions |
| 79 | +#define EMSDP_RESET_EXCP (0) |
| 80 | +#define EMSDP_MEMORY_ERROR_EXCP (1) |
| 81 | +#define EMSDP_INSTRUCTION_ERROR_EXCP (2) |
| 82 | +#define EMSDP_EVMACHINECHECK_EXCP (3) |
| 83 | +#define EMSDP_EVITLBMISS_EXCP (4) |
| 84 | +#define EMSDP_EVDTLBMISS_EXCP (5) |
| 85 | +#define EMSDP_EVPROTV_EXCP (6) |
| 86 | +#define EMSDP_EVPRIVILEGEV_EXCP (7) |
| 87 | +#define EMSDP_EVSWI_EXCP (8) |
| 88 | +#define EMSDP_EVTRAP_EXCP (9) |
| 89 | +#define EMSDP_EVEXTENSION_EXCP (10) |
| 90 | +#define EMSDP_EVDIVZERO_EXCP (11) |
| 91 | +#define EMSDP_EVDCERROR_EXCP (12) |
| 92 | +#define EMSDP_EVMALIGNED_EXCP (13) |
| 93 | + |
| 94 | +//ARC External private interrupts (low interrupts) |
| 95 | +#define EMSDP_TIMER0_EXCP (16) |
| 96 | +#define EMSDP_TIMER1_EXCP (17) |
| 97 | + |
| 98 | +#define EMSDP_MAX_NUM_EXCP (24) |
| 99 | +#define EMSDP_MAX_NUM_ISR (80) |
| 100 | + |
| 101 | + |
| 102 | +//EMSDP Peripheral Subsystem Interrupt assignments |
| 103 | +#define EMSDP_SPI0_INTR (84) |
| 104 | +#define EMSDP_SPI1_INTR (85) |
| 105 | +#define EMSDP_GPIO_INTR0 (86) |
| 106 | +#define EMSDP_GPIO_INTR1 (87) |
| 107 | +#define EMSDP_GPIO_INTR2 (88) |
| 108 | +#define EMSDP_GPIO_INTR3 (89) |
| 109 | +#define EMSDP_TIMER0_INTR0 (90) |
| 110 | +#define EMSDP_TIMER0_INTR1 (91) |
| 111 | +#define EMSDP_TIMER0_INTR2 (92) |
| 112 | +#define EMSDP_TIMER0_INTR3 (93) |
| 113 | +#define EMSDP_TIMER0_INTR4 (94) |
| 114 | +#define EMSDP_TIMER0_INTR5 (95) |
| 115 | +#define EMSDP_TIMER0_INTR6 (96) |
| 116 | +#define EMSDP_TIMER0_INTR7 (97) |
| 117 | +#define EMSDP_TIMER1_INTR0 (98) |
| 118 | +#define EMSDP_TIMER1_INTR1 (99) |
| 119 | +#define EMSDP_TIMER1_INTR2 (100) |
| 120 | +#define EMSDP_TIMER1_INTR3 (101) |
| 121 | +#define EMSDP_TIMER1_INTR4 (102) |
| 122 | +#define EMSDP_TIMER1_INTR5 (103) |
| 123 | +#define EMSDP_TIMER1_INTR6 (104) |
| 124 | +#define EMSDP_TIMER1_INTR7 (105) |
| 125 | +#define EMSDP_UART_INTR (106) |
| 126 | +#define EMSDP_WDT_INTR (107) |
| 127 | +#define EMSDP_DBG_UART_INTR (108) |
| 128 | +#define EMSDP_SDIO_INTR (109) |
| 129 | +#define EMSDP_REDPINE_SPI_INTR (110) |
| 130 | +#define EMSDP_REDPINE_HOST_WAKEUP (111) |
| 131 | +#define EMSDP_NIST_TRNG_INTR (112) |
| 132 | + |
| 133 | + |
| 134 | +//EMSDP Peripheral Subsystem DMA assignments |
| 135 | +#define UART_DMA_TX (9) |
| 136 | +#define UART_DMA_RX (10) |
| 137 | +#define REDPINE_SPI_DMA_TX (11) |
| 138 | +#define REDPINE_SPI_DMA_RX (12) |
| 139 | +#define FLASH_SPI_DMA_TX (13) |
| 140 | +#define FLASH_SPI_DMA_RX (14) |
| 141 | + |
| 142 | +#endif //__BOARD_EMSDP_H__ |
0 commit comments