Safer usage of 5bit register class

Author: Claudiu Zissulescu

gcc/ChangeLog.ARC

@@ -1,3 +1,12 @@
+2013-05-22 Claudiu Zissulescu <[email protected]>
+
+	* config/arc/arc.c (arc_conditional_register_usage): Make sure
+          r30 is fix for the time being.
+	* config/arc/arc.h (AC16_H_REGS): New Register class.
+	* config/arc/arc.md :Use 'h' instead of 'W' for 5bit register
+          class.
+	* config/arc/constraints.md ('h'): New register constraint letter.
+
 2013-05-16 Claudiu Zissulescu <[email protected]>
 
 	* config/arc/arc.c (arc_expand_movmem): Fix computation on

gcc/config/arc/arc.c

@@ -1342,12 +1342,13 @@ arc_conditional_register_usage (void)
   int i;
   int fix_start = 60, fix_end = 55;
 
-  /* For ARCv2 the core register set is changed.*/
   if (TARGET_V2)
     {
+      /* For ARCv2 the core register set is changed.*/
       strcpy(rname29, "ilink");
       strcpy(rname30, "r30");
-    }
+      fixed_regs[30] = call_used_regs[30] = 1;
+   }
   if (TARGET_MUL64_SET)
     {
       fix_start = 57;

gcc/config/arc/arc.h

@@ -535,7 +535,7 @@ if (GET_MODE_CLASS (MODE) == MODE_INT		\
    27    - frame pointer
    28    - stack pointer
    29    - ilink1
-   30    - ilink2
+   30    - ilink2 (general purpose register ARCv2)
    31    - return address register
 
    By default, the extension registers are not available.  */
@@ -601,7 +601,7 @@ if (GET_MODE_CLASS (MODE) == MODE_INT		\
 /* If defined, an initializer for a vector of integers, containing the
    numbers of hard registers in the order in which GCC should
    prefer to use them (from most preferred to least).  */
-#define REG_ALLOC_ORDER \
+#define REG_ALLOC_ORDER							\
 { 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 1,			\
   16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 				\
   32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,	\
@@ -631,7 +631,7 @@ extern unsigned int arc_mode_class[];
    MODE2)' must be zero.  */
 
 /* Tie QI/HI/SI modes together.  */
-#define MODES_TIEABLE_P(MODE1, MODE2) \
+#define MODES_TIEABLE_P(MODE1, MODE2)		\
 (GET_MODE_CLASS (MODE1) == MODE_INT		\
  && GET_MODE_CLASS (MODE2) == MODE_INT		\
  && GET_MODE_SIZE (MODE1) <= UNITS_PER_WORD	\
@@ -694,6 +694,7 @@ enum reg_class
    ALL_CORE_REGS,		/* 'Rac' */
    R0R3_CODE_DENSITY_REGS,      /* 'Rcd' */
    R0R1_CODE_DENSITY_REGS,      /* 'Rsd' */
+   AC16_H_REGS,                 /* 'h' */
    ALL_REGS,
    LIM_REG_CLASSES
 };
@@ -722,6 +723,7 @@ enum reg_class
   "CHEAP_CORE_REGS",	    \
   "R0R3_CODE_DENSITY_REGS", \
   "R0R1_CODE_DENSITY_REGS", \
+  "AC16_H_REGS",	    \
   "ALL_CORE_REGS",	    \
   "ALL_REGS"          	    \
 }
@@ -756,6 +758,7 @@ enum reg_class
   {0xffffffff, 0xdfffffff, 0x00000000, 0x00000000, 0x00000000},      /* 'Rac', r0-r60, ap, pcl */ \
   {0x0000000f, 0x00000000, 0x00000000, 0x00000000, 0x00000000},      /* 'Rcd', r0-r3 */ \
   {0x00000003, 0x00000000, 0x00000000, 0x00000000, 0x00000000},      /* 'Rsd', r0-r1 */ \
+  {0x9fffffff, 0x00000000, 0x00000000, 0x00000000, 0x00000000},      /* 'h',  r0-28, r30 */ \
   {0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff, 0x0003ffff}       /* All Registers */		\
 }
 
@@ -794,9 +797,9 @@ extern enum reg_class arc_regno_reg_class[];
    or a pseudo reg currently allocated to a suitable hard reg.
    Since they use reg_renumber, they are safe only once reg_renumber
    has been allocated, which happens in local-alloc.c.  */
-#define REGNO_OK_FOR_BASE_P(REGNO) \
-((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) ||\
- (unsigned) reg_renumber[REGNO] < 29)
+#define REGNO_OK_FOR_BASE_P(REGNO)					\
+  ((REGNO) < 29 || ((REGNO) == ARG_POINTER_REGNUM) || ((REGNO) == 63) || \
+   (unsigned) reg_renumber[REGNO] < 29)
 
 #define REGNO_OK_FOR_INDEX_P(REGNO) REGNO_OK_FOR_BASE_P(REGNO)
 
@@ -805,17 +808,17 @@ extern enum reg_class arc_regno_reg_class[];
    In general this is just CLASS; but on some machines
    in some cases it is preferable to use a more restrictive class.  */
 
-#define PREFERRED_RELOAD_CLASS(X, CLASS) \
+#define PREFERRED_RELOAD_CLASS(X, CLASS)	\
   arc_preferred_reload_class((X), (CLASS))
 
   extern enum reg_class arc_preferred_reload_class (rtx, enum reg_class);
 
 /* Return the maximum number of consecutive registers
    needed to represent mode MODE in a register of class CLASS.  */
 
-#define CLASS_MAX_NREGS(CLASS, MODE) \
-(( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1: \
-((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
+#define CLASS_MAX_NREGS(CLASS, MODE)					\
+  (( GET_MODE_SIZE (MODE) == 16 && CLASS == SIMD_VR_REGS) ? 1:		\
+   ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD))
 
 #define SMALL_INT(X) ((unsigned) ((X) + 0x100) < 0x200)
 #define SMALL_INT_RANGE(X, OFFSET, SHIFT) \

gcc/config/arc/arc.md

@@ -593,8 +593,8 @@
 ; The iscompact attribute allows the epilogue expander to know for which
 ; insns it should lengthen the return insn.
 (define_insn "*movqi_insn"
-  [(set (match_operand:QI 0 "move_dest_operand" "=Rcq,Rcq#q,    w,   W, w, w,???w, w,Rcq,  S,!*x,r,m,???m")
-	(match_operand:QI 1 "move_src_operand"   " cL,   cP,Rcq#q,WCm1,cL, I,?Rac,?i,  T,Rcq,Usd,m,c,?Rac"))]
+  [(set (match_operand:QI 0 "move_dest_operand" "=Rcq,Rcq#q,    w,   h, w, w,???w, w,Rcq,  S,!*x,r,m,???m")
+	(match_operand:QI 1 "move_src_operand"   " cL,   cP,Rcq#q,hCm1,cL, I,?Rac,?i,  T,Rcq,Usd,m,c,?Rac"))]
   "register_operand (operands[0], QImode)
    || register_operand (operands[1], QImode)"
   "@
@@ -624,8 +624,8 @@
   "if (prepare_move_operands (operands, HImode)) DONE;")
 
 (define_insn "*movhi_insn"
-  [(set (match_operand:HI 0 "move_dest_operand" "=Rcq,Rcq#q,    w,   W, w,w,???w,Rcq#q, w,Rcq,  S,r,m,???m,VUsc,VUsc")
-	(match_operand:HI 1 "move_src_operand"    "cL,   cP,Rcq#q,WCm1,cL,I,?Rac,   ?i,?i,  T,Rcq,m,c,?Rac, Cm3,   i"))]
+  [(set (match_operand:HI 0 "move_dest_operand" "=Rcq,Rcq#q,    w,   h, w,w,???w,Rcq#q, w,Rcq,  S,r,m,???m,VUsc,VUsc")
+	(match_operand:HI 1 "move_src_operand"    "cL,   cP,Rcq#q,hCm1,cL,I,?Rac,   ?i,?i,  T,Rcq,m,c,?Rac, Cm3,   i"))]
   "register_operand (operands[0], HImode)
    || register_operand (operands[1], HImode)
    || (CONSTANT_P (operands[1])
@@ -670,8 +670,8 @@
 ; insns it should lengthen the return insn.
 ; N.B. operand 1 of alternative 7 expands into pcl,symbol@gotpc .
 (define_insn "*movsi_insn"                       ;   0     1     2    3  4 5   6    7   8   9    10   11  12  13     14     15  16  17  18  19  20  21   22   23   24
-  [(set (match_operand:SI 0 "move_dest_operand"  "=Rcq,Rcq#q,    w,   W, w,w,  w,???w, ?w,  w,Rcq#q,   w,Rcq,  S,   Us<,RcqRck,!*x,!*Rsd,!*Rcd,  r,Usd,  m,???m,VUsc,VUsc")
-	(match_operand:SI 1 "move_src_operand"     "cL,   cP,Rcq#q,WCm1,cL,I,Crr,?Rac,Cpc,Clb, ?Cal,?Cal,Uts,Rcq,RcqRck,   Us>,Usd,  Usd,  Ucd,  m,!*x,  c,?Rac, Cm3, C32"))]
+  [(set (match_operand:SI 0 "move_dest_operand"  "=Rcq,Rcq#q,    w,   h, w,w,  w,???w, ?w,  w,Rcq#q,   w,Rcq,  S,   Us<,RcqRck,!*x,!*Rsd,!*Rcd,  r,Usd,  m,???m,VUsc,VUsc")
+	(match_operand:SI 1 "move_src_operand"     "cL,   cP,Rcq#q,hCm1,cL,I,Crr,?Rac,Cpc,Clb, ?Cal,?Cal,Uts,Rcq,RcqRck,   Us>,Usd,  Usd,  Ucd,  m,!*x,  c,?Rac, Cm3, C32"))]
   "register_operand (operands[0], SImode)
    || register_operand (operands[1], SImode)
    || (CONSTANT_P (operands[1])
@@ -1046,8 +1046,8 @@
   "if (prepare_move_operands (operands, SFmode)) DONE;")
 
 (define_insn "*movsf_insn"
-  [(set (match_operand:SF 0 "move_dest_operand" "=   W,w,w,r,m")
-	(match_operand:SF 1 "move_src_operand"   "WCm1,c,E,m,c"))]
+  [(set (match_operand:SF 0 "move_dest_operand" "=   h,w,w,r,m")
+	(match_operand:SF 1 "move_src_operand"   "hCm1,c,E,m,c"))]
   "(register_operand (operands[0], SFmode)
    || register_operand (operands[1], SFmode))
    && !(register_operand (operands[1], SFmode) && REGNO(operands[1]) == 58)"
@@ -1650,7 +1650,7 @@
 ;  register class 'W' instead of 'w'.
 (define_insn_and_split "*addsi3_mixed"
   ;;                                                      0       1    2    3   4   5   6     7    8   9   a    b     c   d e   f  10  11  12
-  [(set (match_operand:SI 0 "dest_reg_operand"          "=Rcq#q,Rcq,   W,!*Rsd,Rcq,Rcb,Rcq, Rcqq,Rcqq,Rcw,Rcw, Rcw,    W,  W,W,  W,Rcqq,Rcw,  W")
+  [(set (match_operand:SI 0 "dest_reg_operand"          "=Rcq#q,Rcq,   h,!*Rsd,Rcq,Rcb,Rcq, Rcqq,Rcqq,Rcw,Rcw, Rcw,    W,  W,W,  W,Rcqq,Rcw,  W")
 	(plus:SI (match_operand:SI 1 "register_operand" "%0,      c,   0, Rcqq,  0,  0,Rcb, Rcqq,   0,  0,  c,   0,    c,  c,0,  0,   0,  0,  c")
 		 (match_operand:SI 2 "nonmemory_operand" "cL,     0, Cm1,    L,CL2,Csp,CM4,RcqqK,  cO, cL,  0,cCca,cLCmL,Cca,I,C2a, Cal,Cal,Cal")))]
   ""
@@ -3319,7 +3319,7 @@
 ;; modifed cc user if second, but not first operand is a compact register.
 (define_insn "cmpsi_cc_insn_mixed"
   [(set (reg:CC CC_REG)
-	(compare:CC (match_operand:SI 0 "register_operand"  "Rcq#q,  W, c, c, qRcq, c")
+	(compare:CC (match_operand:SI 0 "register_operand"  "Rcq#q,  h, c, c, qRcq, c")
 		    (match_operand:SI 1 "nonmemory_operand" "   cO,Cm1,cI,cL,  Cal, Cal")))]
   ""
   "cmp%? %0,%B1%&"
@@ -3405,7 +3405,7 @@
 
 (define_insn "*cmpsi_cc_c_insn"
   [(set (reg:CC_C CC_REG)
-	(compare:CC_C (match_operand:SI 0 "register_operand"  "Rcqq,  W, c,Rcqq,  c")
+	(compare:CC_C (match_operand:SI 0 "register_operand"  "Rcqq,  h, c,Rcqq,  c")
 		      (match_operand:SI 1 "nonmemory_operand" "  cO,Cm1,cI, Cal,Cal")))]
   ""
   "cmp%? %0,%S1%&"
@@ -3502,7 +3502,7 @@
   [(cond_exec
      (ne (match_operand:CC_Z 2 "cc_use_register"    "Rcc,  Rcc,  Rcc,Rcc, Rcc,Rcc") (const_int 0))
      (set (match_operand:SI 0 "dest_reg_operand" "=Rcq#q,Rcq#q,Rcq#q,  w,???w,w")
-	  (match_operand:SI 1 "nonmemory_operand"   "C_0,    W, ?Cal, Lc,?Rac,?Cal")))]
+	  (match_operand:SI 1 "nonmemory_operand"   "C_0,    h, ?Cal, Lc,?Rac,?Cal")))]
   ""
   "@
 	* current_insn_predicate = 0; return \"sub%?.ne %0,%0,%0%&\";

gcc/config/arc/constraints.md

@@ -459,3 +459,8 @@
 (define_register_constraint "Rsd" "R0R1_CODE_DENSITY_REGS"
   "@internal
    core register @code{r0}-@code{r1}")
+
+(define_register_constraint "h" "AC16_H_REGS"
+  "5-bit h register set except @code{r30} and @code{r29}: @code{r0}-@code{r31}, nonfixed core register")
+
+