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Commit 331e9d1

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author
Claudiu Zissulescu
committed
Change the way how mul/mulu are modeled for arc600
1 parent ba6cd07 commit 331e9d1

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3 files changed

+78
-52
lines changed

3 files changed

+78
-52
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‎gcc/config/arc/arc.md‎

Lines changed: 46 additions & 52 deletions
Original file line numberDiff line numberDiff line change
@@ -1902,14 +1902,28 @@
19021902
[(set_attr "is_sfunc" "yes")
19031903
(set_attr "predicable" "yes")])
19041904

1905-
(define_insn "mulsidi_600"
1906-
[(set (reg:DI MUL64_OUT_REG)
1907-
(mult:DI (sign_extend:DI
1908-
(match_operand:SI 0 "register_operand" "Rcq#q,c,c,%c"))
1909-
(sign_extend:DI
1910-
; assembler issue for "I", see mulsi_600
1911-
; (match_operand:SI 1 "register_operand" "Rcq#q,cL,I,Cal"))))]
1912-
(match_operand:SI 1 "register_operand" "Rcq#q,cL,L,C32"))))]
1905+
1906+
(define_insn_and_split "mulsidi_600"
1907+
[(set (match_operand:DI 0 "nonimmediate_operand" "=mc,mc,mc,mc")
1908+
(mult:DI (sign_extend:DI (match_operand:SI 1 "register_operand" "Rcq#q, c, c,%c"))
1909+
(sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "Rcq#q,cL, L,C32"))))
1910+
(clobber (reg:DI MUL64_OUT_REG))]
1911+
"TARGET_MUL64_SET && !TARGET_V2"
1912+
"#"
1913+
"TARGET_MUL64_SET && !TARGET_V2"
1914+
[(const_int 0)]
1915+
"emit_insn (gen_mul64 (operands[1], operands[2]));
1916+
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
1917+
DONE;
1918+
"
1919+
[(set_attr "type" "multi")
1920+
(set_attr "length" "8")])
1921+
1922+
(define_insn "mul64"
1923+
[(unspec [(match_operand:SI 0 "register_operand" "Rcq#q, c,c,%c")
1924+
(match_operand:SI 1 "nonmemory_operand" "Rcq#q,cL,L,C32")]
1925+
UNSPEC_MUL64)
1926+
(clobber (reg:DI MUL64_OUT_REG))]
19131927
"TARGET_MUL64_SET"
19141928
"mul64%? \t0, %0, %1%&"
19151929
[(set_attr "length" "*,4,4,8")
@@ -1918,14 +1932,28 @@
19181932
(set_attr "predicable" "yes,yes,no,yes")
19191933
(set_attr "cond" "canuse,canuse,canuse_limm,canuse")])
19201934

1921-
(define_insn "umulsidi_600"
1922-
[(set (reg:DI MUL64_OUT_REG)
1923-
(mult:DI (zero_extend:DI
1924-
(match_operand:SI 0 "register_operand" "c,c,%c"))
1925-
(sign_extend:DI
1926-
; assembler issue for "I", see mulsi_600
1927-
; (match_operand:SI 1 "register_operand" "cL,I,Cal"))))]
1928-
(match_operand:SI 1 "register_operand" "cL,L,C32"))))]
1935+
1936+
(define_insn_and_split "umulsidi_600"
1937+
[(set (match_operand:DI 0 "nonimmediate_operand" "=mc,mc,mc")
1938+
(mult:DI (zero_extend:DI (match_operand:SI 1 "register_operand" "c, c,%c"))
1939+
(sign_extend:DI (match_operand:SI 2 "nonmemory_operand" "cL, L,C32"))))
1940+
(clobber (reg:DI MUL64_OUT_REG))]
1941+
"TARGET_MUL64_SET && !TARGET_V2"
1942+
"#"
1943+
"TARGET_MUL64_SET && !TARGET_V2"
1944+
[(const_int 0)]
1945+
"emit_insn (gen_mulu64 (operands[1], operands[2]));
1946+
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
1947+
DONE;
1948+
"
1949+
[(set_attr "type" "umulti")
1950+
(set_attr "length" "8")])
1951+
1952+
(define_insn "mulu64"
1953+
[(unspec [(match_operand:SI 0 "register_operand" "c,c,%c")
1954+
(match_operand:SI 1 "nonmemory_operand" "cL,L,C32")]
1955+
UNSPEC_MULU64)
1956+
(clobber (reg:DI MUL64_OUT_REG))]
19291957
"TARGET_MUL64_SET"
19301958
"mulu64%? \t0, %0, %1%&"
19311959
[(set_attr "length" "4,4,8")
@@ -1998,9 +2026,7 @@
19982026
}
19992027
else if (TARGET_MUL64_SET)
20002028
{
2001-
operands[2] = force_reg (SImode, operands[2]);
2002-
emit_insn (gen_mulsidi_600 (operands[1], operands[2]));
2003-
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
2029+
emit_insn (gen_mulsidi_600 (operands[0], operands[1], operands[2]));
20042030
DONE;
20052031
}
20062032
else if (TARGET_MULMAC_32BY16_SET)
@@ -2239,9 +2265,7 @@
22392265
}
22402266
else if (TARGET_MUL64_SET)
22412267
{
2242-
operands[2] = force_reg (SImode, operands[2]);
2243-
emit_insn (gen_umulsidi_600 (operands[1], operands[2]));
2244-
emit_move_insn (operands[0], gen_rtx_REG (DImode, MUL64_OUT_REG));
2268+
emit_insn (gen_umulsidi_600 (operands[0], operands[1], operands[2]));
22452269
DONE;
22462270
}
22472271
else if (TARGET_MULMAC_32BY16_SET)
@@ -4336,36 +4360,6 @@
43364360
[(set_attr "length" "4,8,4")
43374361
(set_attr "type" "two_cycle_core,two_cycle_core,two_cycle_core")])
43384362

4339-
;; FIXME: an intrinsic for multiply is daft. Can we remove this?
4340-
(define_insn "mul64"
4341-
[(unspec [(match_operand:SI 0 "general_operand" "q,r,r,%r")
4342-
(match_operand:SI 1 "general_operand" "q,rL,I,Cal")]
4343-
UNSPEC_MUL64)]
4344-
"TARGET_MUL64_SET"
4345-
"@
4346-
mul64%? \t0, %0, %1%&
4347-
mul64%? \t0, %0, %1
4348-
mul64 \t0, %0, %1
4349-
mul64%? \t0, %0, %S1"
4350-
[(set_attr "length" "2,4,4,8")
4351-
(set_attr "iscompact" "true,false,false,false")
4352-
(set_attr "type" "binary,binary,binary,binary")
4353-
(set_attr "cond" "canuse,canuse, nocond, canuse")])
4354-
4355-
(define_insn "mulu64"
4356-
[(unspec [(match_operand:SI 0 "general_operand" "%r,r,r,r")
4357-
(match_operand:SI 1 "general_operand" "rL,I,r,Cal")]
4358-
UNSPEC_MULU64)]
4359-
"TARGET_MUL64_SET"
4360-
"@
4361-
mulu64%? \t0, %0, %1
4362-
mulu64 \t0, %0, %1
4363-
mulu64 \t0, %0, %1
4364-
mulu64%? \t0, %0, %S1"
4365-
[(set_attr "length" "4,4,4,8")
4366-
(set_attr "type" "binary,binary,binary,binary")
4367-
(set_attr "cond" "canuse,nocond,nocond,canuse")])
4368-
43694363
(define_insn "divaw"
43704364
[(set (match_operand:SI 0 "dest_reg_operand" "=&w,&w,&w")
43714365
(unspec:SI [(div:SI (match_operand:SI 1 "general_operand" "r,Cal,r")

‎gcc/testsuite/gcc.target/arc/builtin_mul64.c‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
/* Check that we use the ffs insn by checking assembler output. */
2+
/* { dg-do compile } */
3+
/* { dg-skip-if "Avoid multiple cpu option warning" { "arc*-*-*" } { "-mcpu=*" "-mav*" "-mA*" } { "" } } */
4+
/* { dg-options "-O2 -mmul64 -mcpu=ARC600" } */
5+
/* { dg-final { scan-assembler "\tmul64.*0, r0, r1" } } */
6+
/* { dg-final { scan-assembler "\tmul64.*0, r0, 16" } } */
7+
void foo (int x, int y)
8+
{
9+
__builtin_arc_mul64(x,y);
10+
}
11+
12+
void bar (int x)
13+
{
14+
__builtin_arc_mul64(x, 0x10);
15+
}
16+

‎gcc/testsuite/gcc.target/arc/builtin_mulu64.c‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
/* Check that we use the ffs insn by checking assembler output. */
2+
/* { dg-do compile } */
3+
/* { dg-skip-if "Avoid multiple cpu option warning" { "arc*-*-*" } { "-mcpu=*" "-mav*" "-mA*" } { "" } } */
4+
/* { dg-options "-O2 -mmul64 -mcpu=ARC600" } */
5+
/* { dg-final { scan-assembler "\tmulu64.*0, r0, r1" } } */
6+
/* { dg-final { scan-assembler "\tmulu64.*0, r0, 16" } } */
7+
void foo (int x, int y)
8+
{
9+
__builtin_arc_mulu64(x,y);
10+
}
11+
12+
void bar (int x)
13+
{
14+
__builtin_arc_mulu64(x, 0x10);
15+
}
16+

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