@@ -5250,21 +5250,38 @@ arc_function_args_impl (CUMULATIVE_ARGS *cum,
52505250 {
52515251 reg_idx = cum -> last_reg ; /* for unamed args don't try fill up the reg-holes. */
52525252 nregs = arc_hard_regno_nregs (0 , mode , type ); /* only interested in the number of regs. */
5253- if ((nregs == 2 )
5253+ if ((( nregs == 2 ) || ( nregs == 4 ) )
52545254 && (mode != BLKmode ) /* Only DI-like modes are interesting for us. */
52555255 && (reg_idx & 1 ) /* Only for "non-aligned" registers. */
52565256 && FUNCTION_ARG_REGNO_P (reg_idx )) /* Allow passing partial arguments. */
52575257 {
5258- rtx reg1 = gen_rtx_REG (SImode , reg_idx );
5259- rtx reg2 = gen_rtx_REG (SImode , reg_idx + 1 );
5260- rtvec vec = gen_rtvec (2 , gen_rtx_EXPR_LIST (VOIDmode , reg1 , const0_rtx ),
5261- gen_rtx_EXPR_LIST (VOIDmode , reg2 , GEN_INT (4 )));
5258+ rtx reg [4 ];
5259+ rtvec vec ;
5260+
5261+ if (nregs == 2 )
5262+ {
5263+ reg [0 ] = gen_rtx_REG (SImode , reg_idx );
5264+ reg [1 ] = gen_rtx_REG (SImode , reg_idx + 1 );
5265+ vec = gen_rtvec (2 , gen_rtx_EXPR_LIST (VOIDmode , reg [0 ], const0_rtx ),
5266+ gen_rtx_EXPR_LIST (VOIDmode , reg [1 ], GEN_INT (4 )));
5267+ }
5268+ else
5269+ {
5270+ reg [0 ] = gen_rtx_REG (SImode , reg_idx );
5271+ reg [1 ] = gen_rtx_REG (SImode , reg_idx + 1 );
5272+ reg [2 ] = gen_rtx_REG (SImode , reg_idx + 2 );
5273+ reg [3 ] = gen_rtx_REG (SImode , reg_idx + 3 );
5274+ vec = gen_rtvec (4 , gen_rtx_EXPR_LIST (VOIDmode , reg [0 ], const0_rtx ),
5275+ gen_rtx_EXPR_LIST (VOIDmode , reg [1 ], GEN_INT (4 )),
5276+ gen_rtx_EXPR_LIST (VOIDmode , reg [2 ], GEN_INT (8 )),
5277+ gen_rtx_EXPR_LIST (VOIDmode , reg [3 ], GEN_INT (12 )));
5278+ }
52625279
52635280 if (advance )
52645281 {
52655282 cum -> arg_num += nregs ;
5266- cum -> avail [ reg_idx ] = false;
5267- cum -> avail [reg_idx + 1 ] = false;
5283+ for ( int i = 0 ; i < nregs ; i ++ )
5284+ cum -> avail [reg_idx + i ] = false;
52685285 cum -> last_reg += nregs ;
52695286 }
52705287
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