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| 1 | +/* |
| 2 | + * Copyright (C) 2013 Synopsys, Inc. (www.synopsys.com) |
| 3 | + * |
| 4 | + * This program is free software; you can redistribute it and/or modify |
| 5 | + * it under the terms of the GNU General Public License version 2 as |
| 6 | + * published by the Free Software Foundation. |
| 7 | + */ |
| 8 | + |
| 9 | +/ { |
| 10 | + fpga { |
| 11 | + compatible = "simple-bus"; |
| 12 | + #address-cells = <1>; |
| 13 | + #size-cells = <1>; |
| 14 | + #interrupt-cells = <1>; |
| 15 | + ranges = <0x00000000 0xe0000000 0x10000000>; |
| 16 | + interrupt-parent = <&fpga_intc>; |
| 17 | + |
| 18 | + clocks { |
| 19 | + i2cclk: i2cclk { |
| 20 | + compatible = "fixed-clock"; |
| 21 | + clock-frequency = <50000000>; |
| 22 | + #clock-cells = <0>; |
| 23 | + }; |
| 24 | + |
| 25 | + apbclk: apbclk { |
| 26 | + compatible = "fixed-clock"; |
| 27 | + clock-frequency = <50000000>; |
| 28 | + #clock-cells = <0>; |
| 29 | + }; |
| 30 | + |
| 31 | + mmcclk: mmcclk { |
| 32 | + compatible = "fixed-clock"; |
| 33 | + clock-frequency = <50000000>; |
| 34 | + #clock-cells = <0>; |
| 35 | + }; |
| 36 | + }; |
| 37 | + |
| 38 | + fpga_intc: dw-apb-ictl@0x12000 { |
| 39 | + #interrupt-cells = <1>; |
| 40 | + compatible = "snps,dw-apb-ictl"; |
| 41 | + reg = < 0x12000 0x200 >; |
| 42 | + interrupt-controller; |
| 43 | + interrupt-parent = <&gpio_intc>; |
| 44 | + /* gpio[12] is input for interrupts from FPGA */ |
| 45 | + /* first pin is #10, so interrupt idx 2 */ |
| 46 | + interrupts = < 12 >; |
| 47 | + }; |
| 48 | + |
| 49 | + ethernet@0x18000 { |
| 50 | + #interrupt-cells = <1>; |
| 51 | + compatible = "snps,dwmac"; |
| 52 | + reg = < 0x18000 0x2000 >; |
| 53 | + interrupts = < 4 >; |
| 54 | + interrupt-names = "macirq"; |
| 55 | + phy-mode = "rgmii"; |
| 56 | + snps,phy-addr = < 1 >; |
| 57 | + snps,pbl = < 32 >; |
| 58 | + clocks = <&apbclk>; |
| 59 | + clock-names = "stmmaceth"; |
| 60 | + }; |
| 61 | + |
| 62 | + ehci@0x40000 { |
| 63 | + compatible = "snps,h20apb-ehci"; |
| 64 | + reg = < 0x40000 0x100 >; |
| 65 | + interrupts = < 8 >; |
| 66 | + }; |
| 67 | + |
| 68 | + /* ohci@0x60000 { |
| 69 | + compatible = "snps,h20apb-ohci"; |
| 70 | + reg = < 0x60000 0x100 >; |
| 71 | + interrupts = < 8 >; |
| 72 | + }; */ |
| 73 | + |
| 74 | + mmc@0x15000 { |
| 75 | + compatible = "snps,dw-mshc"; |
| 76 | + reg = < 0x15000 0x400 >; |
| 77 | + num-slots = < 1 >; |
| 78 | + fifo-depth = < 16 >; |
| 79 | + card-detect-delay = < 200 >; |
| 80 | + clocks = <&apbclk>, <&mmcclk>; |
| 81 | + clock-names = "biu", "ciu"; |
| 82 | + interrupts = < 7 >; |
| 83 | + bus-width = < 4 >; |
| 84 | + }; |
| 85 | + |
| 86 | + uart@0x20000 { |
| 87 | + compatible = "snps,dw-apb-uart"; |
| 88 | + reg = <0x20000 0x100>; |
| 89 | + clock-frequency = <33333333>; |
| 90 | + interrupts = <17>; |
| 91 | + baud = <115200>; |
| 92 | + reg-shift = <2>; |
| 93 | + reg-io-width = <4>; |
| 94 | + }; |
| 95 | + |
| 96 | + uart@0x21000 { |
| 97 | + compatible = "snps,dw-apb-uart"; |
| 98 | + reg = <0x21000 0x100>; |
| 99 | + clock-frequency = <33333333>; |
| 100 | + interrupts = <18>; |
| 101 | + baud = <115200>; |
| 102 | + reg-shift = <2>; |
| 103 | + reg-io-width = <4>; |
| 104 | + }; |
| 105 | + |
| 106 | + uart@0x22000 { |
| 107 | + compatible = "snps,dw-apb-uart"; |
| 108 | + reg = <0x22000 0x100>; |
| 109 | + clock-frequency = <33333333>; |
| 110 | + interrupts = <19>; |
| 111 | + baud = <115200>; |
| 112 | + reg-shift = <2>; |
| 113 | + reg-io-width = <4>; |
| 114 | + }; |
| 115 | + |
| 116 | + i2c@0x1d000 { |
| 117 | + compatible = "snps,designware-i2c"; |
| 118 | + reg = <0x1d000 0x100>; |
| 119 | + clock-frequency = <400000>; |
| 120 | + clocks = <&i2cclk>; |
| 121 | + interrupts = <14>; |
| 122 | + }; |
| 123 | + |
| 124 | + i2c@0x1e000 { |
| 125 | + compatible = "snps,designware-i2c"; |
| 126 | + reg = <0x1e000 0x100>; |
| 127 | + clock-frequency = <400000>; |
| 128 | + clocks = <&i2cclk>; |
| 129 | + interrupts = <15>; |
| 130 | + }; |
| 131 | + |
| 132 | + i2c@0x1f000 { |
| 133 | + compatible = "snps,designware-i2c"; |
| 134 | + reg = <0x1f000 0x100>; |
| 135 | + clock-frequency = <400000>; |
| 136 | + clocks = <&i2cclk>; |
| 137 | + interrupts = <16>; |
| 138 | + }; |
| 139 | + |
| 140 | + }; |
| 141 | +}; |
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