7575
7676static int l2_line_sz ;
7777int ioc_exists ;
78+ volatile int slc_enable = 1 ;
7879
7980void (* _cache_line_loop_ic_fn )(unsigned long paddr , unsigned long vaddr ,
8081 unsigned long sz , const int cacheop );
@@ -984,6 +985,20 @@ void arc_cache_init(void)
984985 }
985986 }
986987
988+ if (is_isa_arcv2 () && l2_line_sz && !slc_enable ) {
989+
990+ /* IM set : flush before invalidate */
991+ write_aux_reg (ARC_REG_SLC_CTRL ,
992+ read_aux_reg (ARC_REG_SLC_CTRL ) | SLC_CTRL_IM );
993+
994+ write_aux_reg (ARC_REG_SLC_INVALIDATE , 1 );
995+
996+ /* Important to wait for flush to complete */
997+ while (read_aux_reg (ARC_REG_SLC_CTRL ) & SLC_CTRL_BUSY );
998+ write_aux_reg (ARC_REG_SLC_CTRL ,
999+ read_aux_reg (ARC_REG_SLC_CTRL ) | SLC_CTRL_DISABLE );
1000+ }
1001+
9871002 if (is_isa_arcv2 () && ioc_exists ) {
9881003 /* IO coherency base - 0x8z */
9891004 write_aux_reg (ARC_REG_IO_COH_AP0_BASE , 0x80000 );
@@ -997,7 +1012,7 @@ void arc_cache_init(void)
9971012 __dma_cache_wback_inv = __dma_cache_wback_inv_ioc ;
9981013 __dma_cache_inv = __dma_cache_inv_ioc ;
9991014 __dma_cache_wback = __dma_cache_wback_ioc ;
1000- } else if (is_isa_arcv2 () && l2_line_sz ) {
1015+ } else if (is_isa_arcv2 () && l2_line_sz && slc_enable ) {
10011016 __dma_cache_wback_inv = __dma_cache_wback_inv_slc ;
10021017 __dma_cache_inv = __dma_cache_inv_slc ;
10031018 __dma_cache_wback = __dma_cache_wback_slc ;
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