Set up exception table base address in AArch32

The exception vector table base address can be different from 0x0 in
AArch32 architectures starting from Armv7. In these cases, the register
VBAR has the address.

This patch initializes VBAR with this base address. So if startup code
wants to place the exception vector table at an arbitrary address,
exception handling will continue to work.

Author: vhscampos

picocrt/machine/arm/crt0.c

@@ -232,6 +232,8 @@ _set_stacks(void)
  * and then branches here.
  */
 
+extern void __vector_table(void);
+
 static _Noreturn __attribute__((used)) __section(".init") void
 _cstart(void)
 {
@@ -255,6 +257,12 @@ _cstart(void)
 	__asm__("vmsr fpexc, %0" : : "r" (0x40000000));
 #endif
 
+/* Set up exception table base address (register VBAR_ELx).
+   Architectures earlier than v7 have the base address fixed. */
+#if __ARM_ARCH >= 7
+    __asm__("mcr p15, #0, %0, c12, c0, 0" : : "r"(__vector_table) :);
+#endif
+
 #ifdef _PICOCRT_ENABLE_MMU
 
 #if __ARM_ARCH >= 7 && __ARM_ARCH_PROFILE != 'R'