target/arc: remove memory/register access helpers

This commit removes the {get,set}{Memory,Register} macros, as well as a
couple of smaller ones, from semfunc-helper.h, and substitutes their
contents directly into semfunc-v{2,3}.c. This is done to increase code
transparency and to make arc_gen_*() function bodies more uniform.

Signed-off-by: Artemiy Volkov <[email protected]>

Author: artemiy-volkov

target/arc/semfunc-helper.c

@@ -196,44 +196,6 @@ gen_branch(DisasCtxt *ctx, TCGv target)
     }
 }
 
-#define MEMIDX (ctx->mem_idx)
-
-#ifdef TARGET_ARC32
-const MemOp memop_for_size_sign[2][3] = {
-    { MO_UL, MO_UB, MO_UW }, /* non sign-extended */
-    { MO_UL, MO_SB, MO_SW } /* sign-extended */
-};
-#endif
-
-#ifdef TARGET_ARC64
-const MemOp memop_for_size_sign[2][4] = {
-    { MO_UL, MO_UB, MO_UW, MO_UQ }, /* non sign-extended */
-    { MO_SL, MO_SB, MO_SW, MO_SQ } /* sign-extended */
-};
-#endif
-
-void arc_gen_set_memory(const DisasCtxt *ctx, TCGv vaddr, int size,
-        TCGv src, bool sign_extend)
-{
-#ifdef TARGET_ARC32
-    assert(size != 0x3);
-#endif
-
-    tcg_gen_qemu_st_tl(src, vaddr, MEMIDX,
-                       memop_for_size_sign[sign_extend][size]);
-}
-
-void arc_gen_get_memory(const DisasCtxt *ctx, TCGv dest, TCGv vaddr,
-        int size, bool sign_extend)
-{
-#ifdef TARGET_ARC32
-    assert(size != 0x3);
-#endif
-
-    tcg_gen_qemu_ld_tl(dest, vaddr, MEMIDX,
-                       memop_for_size_sign[sign_extend][size]);
-}
-
 void arc_gen_no_further_loads_pending(const DisasCtxt *ctx, TCGv ret)
 {
     /* TODO: To complete on SMP support. */
@@ -318,53 +280,27 @@ void arc_gen_extract_bits(TCGv ret, TCGv a, TCGv start, TCGv end)
     tcg_temp_free(tmp1);
 }
 
-void arc_gen_get_register(TCGv ret, enum arc_registers reg)
+/* TODO: Get this from props ... */
+void arc_has_interrupts(const DisasCtxt *ctx, TCGv ret)
 {
-    switch (reg) {
-    case R_SP:
-        tcg_gen_mov_tl(ret, cpu_sp);
-        break;
-    case R_STATUS32:
-        gen_helper_get_status32(ret, cpu_env);
-        break;
-    case R_ACCLO:
-        tcg_gen_mov_tl(ret, cpu_acclo);
-        break;
-    case R_ACCHI:
-        tcg_gen_mov_tl(ret, cpu_acchi);
-        break;
-    default:
-        g_assert_not_reached();
-    }
+    tcg_gen_movi_tl(ret, 1);
 }
 
+#ifdef TARGET_ARC32
+const MemOp memop_for_size_sign[2][3] = {
+    { MO_UL, MO_UB, MO_UW }, /* non sign-extended */
+    { MO_UL, MO_SB, MO_SW } /* sign-extended */
+};
+#endif
 
-void arc_gen_set_register(enum arc_registers reg, TCGv value)
-{
-    switch (reg) {
-    case R_SP:
-        tcg_gen_mov_tl(cpu_sp, value);
-        break;
-    case R_STATUS32:
-        gen_helper_set_status32(cpu_env, value);
-        break;
-    case R_ACCLO:
-        tcg_gen_mov_tl(cpu_acclo, value);
-        break;
-    case R_ACCHI:
-        tcg_gen_mov_tl(cpu_acchi, value);
-        break;
-    default:
-        g_assert_not_reached();
-    }
-}
+#ifdef TARGET_ARC64
+const MemOp memop_for_size_sign[2][4] = {
+    { MO_UL, MO_UB, MO_UW, MO_UQ }, /* non sign-extended */
+    { MO_SL, MO_SB, MO_SW, MO_SQ } /* sign-extended */
+};
+#endif
 
 
-/* TODO: Get this from props ... */
-void arc_has_interrupts(const DisasCtxt *ctx, TCGv ret)
-{
-    tcg_gen_movi_tl(ret, 1);
-}
 
 /*
  ***************************************

target/arc/semfunc-helper.h

@@ -104,22 +104,10 @@ static inline void update_delay_flag(DisasContext *ctx)
 void to_implement(const DisasCtxt *ctx);
 void to_implement_wo_abort(const DisasCtxt *ctx);
 
-void arc_gen_set_memory(
-        const DisasCtxt *ctx, TCGv addr, int size, TCGv src, bool sign_extend);
-#define setMemory(ADDRESS, SIZE, VALUE) \
-    arc_gen_set_memory(ctx, ADDRESS, SIZE, VALUE, getFlagX())
-void arc_gen_get_memory(
-        const DisasCtxt *ctx, TCGv ret, TCGv addr, int size, bool sign_extend);
-#define getMemory(R, ADDRESS, SIZE) \
-    arc_gen_get_memory(ctx, R, ADDRESS, SIZE, getFlagX())
-
-#define getFlagX()  (ctx->insn.x)
 #define getZZFlag() (ctx->insn.zz)
 #define getAAFlag() (ctx->insn.aa)
 
-#define SignExtend(VALUE, SIZE) VALUE
 void arc_gen_no_further_loads_pending(const DisasCtxt *ctx, TCGv ret);
-#define NoFurtherLoadsPending(R)    arc_gen_no_further_loads_pending(ctx, R)
 void arc_gen_set_debug(const DisasCtxt *ctx, bool value);
 #define setDebugLD(A)   arc_gen_set_debug(ctx, A)
 
@@ -273,14 +261,6 @@ void arc_gen_macu(TCGv phi, TCGv b, TCGv c);
 void arc_gen_extract_bits(TCGv ret, TCGv a, TCGv start, TCGv end);
 #define extractBits(R, ELEM, START, END) \
     arc_gen_extract_bits(R, ELEM, START, END)
-void arc_gen_get_register(TCGv ret, enum arc_registers reg);
-#define getRegister(R, REG) arc_gen_get_register(R, REG)
-void arc_gen_set_register(enum arc_registers reg, TCGv value);
-#define setRegister(REG, VALUE) \
-    arc_gen_set_register(REG, VALUE); \
-    if (REG == R_STATUS32) { \
-        ret = DISAS_UPDATE; \
-    } \
 
 #define inKernelMode(R) { \
   TCG_GET_STATUS_FIELD_MASKED(R, cpu_pstate, Uf); \
@@ -400,6 +380,14 @@ void tcg_gen_shlfi_tl(TCGv a, int b, TCGv c);
 
 #endif
 
+#ifdef TARGET_ARC32
+extern const MemOp memop_for_size_sign[2][3];
+#endif
+
+#ifdef TARGET_ARC64
+extern const MemOp memop_for_size_sign[2][4];
+#endif
+
 enum ato_op {
     ATO_ADD  = 0b000,
     ATO_OR   = 0b001,