target/arc: implement {push,pop}dl_s instructions

This commit provides support for the translation of push/pop double
instructions (a.k.a. pushdl_s and popdl_s) by decomposing them into two
8-byte writes and adjusting the stack pointer as necessary.

Changes to the decoder, while unnecessary, are made to reflect those to
the opcodes directory in the binutils-gdb repository.

Signed-off-by: Artemiy Volkov <[email protected]>

Author: artemiy-volkov

target/arc/decoder_fragments/arc64-tbl.h

@@ -6587,7 +6587,7 @@
 { "pop_s", 0x0000C0D1, 0x0000F8FF, ARC_OPCODE_ARC32, POP, NONE, { BLINK_S }, { C_AA_AB }},
 
 /* popdl_s RBB_S 11000xxx1101xxx1 */
-{ "popdl_s", 0x0000c0d1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 } }
+{ "popdl_s", 0x0000c0d1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S_CHK }, { 0 } }
 
 /* popl_s RBB_S 11000xxx1100xxx1 */
 { "popl_s", 0x0000c0c1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 } }
@@ -6653,7 +6653,7 @@
 { "push_s", 0x0000C0F1, 0x0000F8FF, ARC_OPCODE_ARC32, PUSH, NONE, { BLINK_S }, { C_AA_AW }},
 
 /* pushdl_s RBB_S 11000xxx1111xxx1 */
-{ "pushdl_s", 0x0000c0f1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 } }
+{ "pushdl_s", 0x0000c0f1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S_CHK }, { 0 } }
 
 /* pushl_s RBB_S 11000xxx1110xxx1 */
 { "pushl_s", 0x0000c0e1, 0x0000f8f1, ARC_OPCODE_ARC64, ARITH, NONE, { RBB_S }, { 0 } }

target/arc/operands.def

@@ -22,6 +22,7 @@ ARC_OPERAND(RA_CHK, 6, 0, 0, ARC_OPERAND_IR, 0)
 ARC_OPERAND(RB, 6, 12, 0, ARC_OPERAND_IR, extract_rb)
 ARC_OPERAND(RB_CHK, 6, 12, 0, ARC_OPERAND_IR, extract_rb)
 ARC_OPERAND(RBB_S, 6, 12, 0, ARC_OPERAND_IR, extract_rbb)
+ARC_OPERAND(RBB_S_CHK, 6, 12, 0, ARC_OPERAND_IR, extract_rbb)
 ARC_OPERAND(RC, 6, 6, 0, ARC_OPERAND_IR, 0)
 ARC_OPERAND(RC_CHK, 6, 6, 0, ARC_OPERAND_IR, 0)
 ARC_OPERAND(RBdup, 6, 12, 0, ARC_OPERAND_IR | ARC_OPERAND_DUPLICATE, extract_rb)

target/arc/semfunc-mapping.def

@@ -402,12 +402,14 @@ SEMANTIC_FUNCTION(SCONDL, 2)
 SEMANTIC_FUNCTION(LDL, 3)
 SEMANTIC_FUNCTION(STL, 3)
 SEMANTIC_FUNCTION(POPL, 1)
+SEMANTIC_FUNCTION(POPDL, 1)
 SEMANTIC_FUNCTION(NORML, 2)
 SEMANTIC_FUNCTION(FLSL, 2)
 SEMANTIC_FUNCTION(FFSL, 2)
 SEMANTIC_FUNCTION(DBNZL, 2)
 SEMANTIC_FUNCTION(SEXWL, 2)
 SEMANTIC_FUNCTION(PUSHL, 1)
+SEMANTIC_FUNCTION(PUSHDL, 1)
 SEMANTIC_FUNCTION(BBIT0L, 3)
 SEMANTIC_FUNCTION(BBIT1L, 3)
 
@@ -509,9 +511,9 @@ MAPPING(tstl, TSTL, 2, 0, 1)
 MAPPING(xbful, XBFUL, 3, 2, 1, 0)
 
 MAPPING(pushl_s, PUSHL, 1, 0)
-MAPPING(pushdl_s, PUSHL, 1, 0)
+MAPPING(pushdl_s, PUSHDL, 1, 0)
 MAPPING(popl_s, POPL, 1, 0)
-MAPPING(popdl_s, POPL, 1, 0)
+MAPPING(popdl_s, POPDL, 1, 0)
 
 MAPPING(bbit0l, BBIT0L, 3, 0, 1, 2)
 MAPPING(bbit1l, BBIT1L, 3, 0, 1, 2)

target/arc/semfunc-v3.c

@@ -12022,6 +12022,40 @@ arc_gen_POPL(DisasCtxt *ctx, TCGv dest)
 
 
 
+/* POPDL
+ * Given an even-numbered register @src, read the 128-bit value at $sp into
+ * @src (low part) and @src+1 (high part), then increment $sp by 16 bytes. As
+ * confirmed using nsim, since ARCv3 is little-endian, the low part should be
+ * popped first. The hardware performs not a single 16-byte operation, but
+ * rather two consecutive 8-byte operations.
+ *
+ * No flags are affected by this instruction.
+ */
+
+int
+arc_gen_POPDL(DisasCtxt *ctx, TCGv dest)
+{
+    TCGv sp = tcg_temp_new();
+    TCGv next_reg = nextReg(dest);
+
+    tcg_gen_mov_tl(sp, cpu_sp);
+
+    tcg_gen_qemu_ld_tl(dest, sp, ctx->mem_idx, MO_UQ);
+    tcg_gen_addi_tl(sp, sp, 8);
+
+    tcg_gen_qemu_ld_tl(next_reg, sp, ctx->mem_idx, MO_UQ);
+    tcg_gen_addi_tl(sp, sp, 8);
+
+    if (dest != cpu_sp) {
+        tcg_gen_mov_tl(cpu_sp, sp);
+    }
+
+    tcg_temp_free(sp);
+
+    return DISAS_NEXT;
+}
+
+
 
 
 /* PUSHL
@@ -12050,6 +12084,38 @@ arc_gen_PUSHL(DisasCtxt *ctx, TCGv src)
 
 
 
+/* PUSHDL
+ * Given an even-numbered register @src, decrement $sp by 16 bytes, then write
+ * the 128-bit value represented by @src (low part) and @src+1 (high part) into
+ * the memory at $sp-16. As confirmed using nsim, since ARCv3 is little-endian,
+ * the high part should be pushed first. The hardware performs not a single
+ * 16-byte operation, but two consecutive 8-byte operations.
+ *
+ * No flags are affected by this instruction.
+ */
+
+int
+arc_gen_PUSHDL(DisasCtxt *ctx, TCGv src)
+{
+    TCGv sp = tcg_temp_new();
+    TCGv next_reg = nextReg(src);
+
+    tcg_gen_mov_tl(sp, cpu_sp);
+    tcg_gen_subi_tl(sp, sp, 16);
+    tcg_gen_qemu_st_tl(src, sp, ctx->mem_idx, MO_UQ);
+
+    tcg_gen_addi_tl(sp, sp, 8);
+    tcg_gen_qemu_st_tl(next_reg, sp, ctx->mem_idx, MO_UQ);
+
+    tcg_gen_subi_tl(cpu_sp, sp, 8);
+
+    tcg_temp_free(sp);
+
+    return DISAS_NEXT;
+}
+
+
+
 
 /* NORML
  *    Variables: @src, @dest