add nonbreaking space between number and unit of measure (riscv#2166)

relates to riscv#2165

Signed-off-by: Kevin Broch <[email protected]>

Author: kbroch-rivosinc

src/supervisor.adoc

@@ -1583,7 +1583,7 @@ algorithm are performed using width PTESIZE.
 [NOTE]
 ====
 This implies, for example, that an Sv48 implementation may not use two
-separate 4B reads to non-atomically access a single 8B PTE, and that A/D
+separate 4{nbsp}B reads to non-atomically access a single 8{nbsp}B PTE, and that A/D
 bit updates performed by the implementation are treated as atomically
 updating the entire PTE, rather than just the A and/or D bit alone (even
 though the PTE value does not otherwise change).

src/zc.adoc

@@ -1151,7 +1151,7 @@ calling the millicode _save/restore_ routines and so may also perform better.
 
 [NOTE]
 ====
-The calls to _<riscv_save_0>/<riscv_restore_0>_ become 64-bit when the target functions are out of the ±1MB range, increasing the prologue/epilogue size to 22-bytes.
+The calls to _<riscv_save_0>/<riscv_restore_0>_ become 64-bit when the target functions are out of the ±1{nbsp}MB range, increasing the prologue/epilogue size to 22-bytes.
 ====
 
 [NOTE]
@@ -2332,7 +2332,7 @@ Table jump allows the linker to replace the following instruction sequences with
 * 32-bit _jal_ ra calls
 * 64-bit _auipc+jr_ calls to fixed locations
 * 64-bit _auipc+jalr ra_ calls to fixed locations
-** The _auipc+jr/jalr_ sequence is used because the offset from the PC is out of the ±1MB range.
+** The _auipc+jr/jalr_ sequence is used because the offset from the PC is out of the ±1{nbsp}MB range.
 
 If a return address stack is implemented, then as _cm.jalt_ is equivalent to _jal ra_, it pushes to the stack.
 

src/zilsd.adoc

@@ -44,8 +44,8 @@ The following table summarizes the required behavior:
 [%header]
 |===
 |Alignment |Word accesses guaranteed atomic? |Can cause misaligned trap?
-|8B |yes |no
-|4B not 8B |yes |yes
+|8{nbsp}B |yes |no
+|4{nbsp}B not 8{nbsp}B |yes |yes
 |else |no | yes
 |===