@@ -147,6 +147,22 @@ As with other architectural mandates, it suffices to appear "as if"
147147harts are synchronized to within one tick of the real-time clock, i.e.,
148148software is unable to observe that there is a greater delta between the
149149real-time clock values observed on two harts.
150+
151+ If, for example, the real-time clock increments at a frequency of 1 GHz, then
152+ all harts must appear to be synchronized to within 1 nsec.
153+ But it is also acceptable for this example implementation to only update the
154+ real-time clock at, say, a frequency of 100 MHz with increments of 10 ticks.
155+ As long as software cannot observe this seeming violation of the above
156+ synchronization requirement, and software always observes time across harts to
157+ be monotonically nondecreasing, then this implementation is compliant.
158+
159+ A platform spec may then, for example, specify an apparent real-time clock
160+ tick frequency (e.g. 1 GHz) and also a minimum update frequency (e.g. 100 MHz)
161+ at which updated time values are guaranteed to be observable by software.
162+ Software may read time more frequently, but it should only observe
163+ monotonically nondecreasing values and it should observe a new value at least
164+ once every 10 ns (corresponding to the 100 MHz update frequency in this
165+ example).
150166====
151167The RDINSTRET pseudoinstruction reads the low XLEN bits of the
152168`instret` CSR, which counts the number of instructions retired by this
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