Change "implementor" to "implementers"; fix a couple typos (riscv#1831)

relates to riscv#1830

Author: kbroch-rivosinc

src/c-st-ext.adoc

@@ -197,7 +197,7 @@ _The standard RISC-V calling convention maps the most frequently used
 floating-point registers to registers `f8` to `f15`, which allows the
 same register decompression decoding as for integer register numbers._
 ====
-((((register source spcifiers, c-ext))))
+((((register source specifiers, c-ext))))
 The formats were designed to keep bits for the two register source
 specifiers in the same place in all instructions, while the destination
 register field can move. When the full 5-bit destination register

src/counters-f.adoc

@@ -48,7 +48,7 @@ is that RDCYCLE is used for performance monitoring along with the other
 performance counters. In particular, where there is one hart/core, one
 would expect cycle-count/instructions-retired to measure CPI for a hart.
 
-Cores don’t have to be exposed to software at all, and an implementor
+Cores don’t have to be exposed to software at all, and an implementer
 might choose to pretend multiple harts on one physical core are running
 on separate cores with one hart/core, and provide separate cycle
 counters for each hart. This might make sense in a simple barrel

src/counters.adoc

@@ -78,7 +78,7 @@ is that RDCYCLE is used for performance monitoring along with the other
 performance counters. In particular, where there is one hart/core, one
 would expect cycle-count/instructions-retired to measure CPI for a hart.
 
-Cores don't have to be exposed to software at all, and an implementor
+Cores don't have to be exposed to software at all, and an implementer
 might choose to pretend multiple harts on one physical core are running
 on separate cores with one hart/core, and provide separate cycle
 counters for each hart. This might make sense in a simple barrel

src/f-st-ext.adoc

@@ -196,7 +196,7 @@ standard, but this decision would have increased hardware cost.
 Moreover, since this feature is optional in the standard, it cannot be
 used in portable code.
 
-Implementors are free to provide a NaN payload propagation scheme as a
+Implementers are free to provide a NaN payload propagation scheme as a
 nonstandard extension enabled by a nonstandard operating mode. However, the canonical NaN scheme described above must always be supported and should be the default mode.
 ====
 '''

src/history.adoc

@@ -36,7 +36,7 @@ sources of commercial ISA implementations, but who are prohibited from
 creating their own clean room implementations. We cannot guarantee that
 all RISC-V implementations will be free of third-party patent
 infringements, but we can guarantee we will not attempt to sue a RISC-V
-implementor.
+implementer.
 * *Commercial ISAs are only popular in certain market domains.* The most
 obvious examples at time of writing are that the ARM architecture is not
 well supported in the server space, and the Intel x86 architecture (or
@@ -129,7 +129,7 @@ overall format of the manual date back to the T0 (Torrent-0) vector
 microprocessor project at UC Berkeley and ICSI, begun in 1992. T0 was a
 vector processor based on the MIPS-II ISA, with Krste Asanović as main
 architect and RTL designer, and Brian Kingsbury and Bertrand Irrisou as
-principal VLSI implementors. David Johnson at ICSI was a major
+principal VLSI implementers. David Johnson at ICSI was a major
 contributor to the T0 ISA design, particularly supervisor mode, and to
 the manual text. John Hauser also provided considerable feedback on the
 T0 ISA design.
@@ -167,8 +167,8 @@ Scale infrastructure but the Maven ISA moved further away from the MIPS
 ISA variant defined in Scale, with a unified floating-point and integer
 register file. Maven was designed to support experimentation with
 alternative data-parallel accelerators. Yunsup Lee was the main
-implementor of the various Maven vector units, while Rimas Avižienis was
-the main implementor of the various Maven scalar units. Yunsup Lee and
+implementer of the various Maven vector units, while Rimas Avižienis was
+the main implementer of the various Maven scalar units. Yunsup Lee and
 Christopher Batten ported GCC to work with the new Maven ISA.
 Christopher Celio provided the initial definition of a traditional
 vector instruction set ("Flood") variant of Maven.

src/m-st-ext.adoc

@@ -119,7 +119,7 @@ We considered raising exceptions on integer divide by zero, with these
 exceptions causing a trap in most execution environments. However, this
 would be the only arithmetic trap in the standard ISA (floating-point
 exceptions set flags and write default values, but do not cause traps)
-and would require language implementors to interact with the execution
+and would require language implementers to interact with the execution
 environment's trap handlers for this case. Further, where language
 standards mandate that a divide-by-zero exception must cause an
 immediate control flow change, only a single branch instruction needs to

src/resources/riscv-spec.bib

@@ -750,7 +750,7 @@ @article{CDPA:16
 
 
 %
-% Block Cipher Specifiations
+% Block Cipher Specifications
 % -----------------------------------------------------------------
 
 @inproceedings{block:prince,

src/scalar-crypto.adoc

@@ -3735,7 +3735,7 @@ A virtual source is not a physical entropy source but provides
 additional protection against covert channels, depletion attacks, and host
 identification in operating environments that can not be entirely trusted
 with direct access to a hardware resource. Despite limited trust,
-implementors should try to guarantee that even such environments have
+implementers should try to guarantee that even such environments have
 sufficient entropy available for secure cryptographic operations.
 
 A virtual source traps access to the `seed` CSR, emulates it, or
@@ -5341,13 +5341,13 @@ function gfmul( x, y) = {
   (if bit_to_bool(y[3]) then xt2(xt2(xt2(x))) else 0x00)
 }
 
-/* 8-bit to 32-bit partial AES Mix Colum - forwards */
+/* 8-bit to 32-bit partial AES Mix Column - forwards */
 val aes_mixcolumn_byte_fwd : bits(8) -> bits(32)
 function aes_mixcolumn_byte_fwd(so) = {
   gfmul(so, 0x3) @ so @ so @ gfmul(so, 0x2)
 }
 
-/* 8-bit to 32-bit partial AES Mix Colum - inverse*/
+/* 8-bit to 32-bit partial AES Mix Column - inverse*/
 val aes_mixcolumn_byte_inv : bits(8) -> bits(32)
 function aes_mixcolumn_byte_inv(so) = {
   gfmul(so, 0xb) @ gfmul(so, 0xd) @ gfmul(so, 0x9) @ gfmul(so, 0xe)