Merge pull request riscv#2131 from davidharrishmc/main

Fixed hyphenation of illegal-instruction exception and virtual-instruction exception

Author: kersten1

src/cmo.adoc

@@ -639,8 +639,8 @@ higher privileged level software may program the CSRs so that `CBO.INVAL`
 either traps or performs a flush operation in a lower privileged level._
 ====
 
-A `CBO.CLEAN` or `CBO.FLUSH` instruction executes or raises an illegal
-instruction or virtual-instruction exception based on the state of the
+A `CBO.CLEAN` or `CBO.FLUSH` instruction executes or raises an illegal-instruction
+or virtual-instruction exception based on the state of the
 `x{csrname}.CBCFE` bits:
 
 [source,sail,subs="attributes+"]

src/indirect-csr.adoc

@@ -99,8 +99,8 @@ value that is not implemented, is UNSPECIFIED.
 [%unbreakable]
 [NOTE]
 ====
-It is expected that implementations will typically raise an illegal
-instruction exception for such accesses, so that, for example, they can
+It is expected that implementations will typically raise an illegal-instruction
+exception for such accesses, so that, for example, they can
 be identified as software bugs. Platform specs, profile specs, and/or
 the Privileged ISA spec may place more restrictions on behavior for such
 accesses.

src/priv-cfi.adoc

@@ -232,7 +232,7 @@ of the faulting instruction to discern whether the fault was caused by a
 non-shadow-stack instruction writing to an SS page (a fatal condition) or by a
 shadow stack instruction to a non-resident page (a recoverable condition). The
 performance-critical nature of operating system page fault handlers necessitates
-triggering an access-fault instead of a page fault, allowing for a
+triggering an access fault instead of a page fault, allowing for a
 straightforward distinction between fatal conditions and recoverable faults.
 
 Operating systems must ensure that no writable, non-shadow-stack alias virtual

src/priv-preface.adoc

@@ -474,8 +474,8 @@ status fields in `mstatus`.
 * The SEIP and UEIP bits in the `mip` CSR have been redefined to support
 software injection of external interrupts.
 * The `mbadaddr` register has been subsumed by a more general `mtval`
-register that can now capture bad instruction bits on an illegal
-instruction fault to speed instruction emulation.
+register that can now capture bad instruction bits on an illegal-instruction
+fault to speed instruction emulation.
 * The machine-mode base-and-bounds translation and protection schemes
 have been removed from the specification as part of moving the virtual
 memory configuration to `sptbr` (now `satp`). Some of the motivation for

src/smcdeleg.adoc

@@ -104,10 +104,9 @@ by extensions Smcsrind/Sscsrind, a virtual-instruction  exception is
 raised for attempts from VS-mode or VU-mode to directly access `vsiselect`
 or `vsireg*`, or attempts from VU-mode to access `siselect` or `sireg*`. Furthermore, while `vsiselect` holds a value in the range 0x40-0x5F:
 
-* An attempt to access any `vsireg*` from M or S mode raises an illegal
-instruction exception.
-* An attempt from VS-mode to access any `sireg*` (really `vsireg*`) raises an illegal-instruction exception if `menvcfg`.CDE = 0, or a virtual
-instruction exception if `menvcfg`.CDE = 1.
+* An attempt to access any `vsireg*` from M or S mode raises an illegal-instruction exception.
+* An attempt from VS-mode to access any `sireg*` (really `vsireg*`) raises an illegal-instruction exception if `menvcfg`.CDE = 0, or a
+virtual-instruction exception if `menvcfg`.CDE = 1.
 
 === Supervisor Counter Inhibit (`scountinhibit`) Register
 
@@ -117,8 +116,8 @@ Smcdeleg/Ssccfg defines a new `scountinhibit` register, a masked alias of
 delegated to S-mode, the associated bits in `scountinhibit` are read-only
 zero.
 
-When `menvcfg`.CDE=0, attempts to access `scountinhibit` raise an illegal
-instruction exception. When Supervisor Counter Delegation
+When `menvcfg`.CDE=0, attempts to access `scountinhibit` raise an illegal-instruction
+exception. When Supervisor Counter Delegation
 is enabled, attempts to access `scountinhibit` from VS-mode or VU-mode
 raise a virtual-instruction  exception.
 

src/smstateen.adoc

@@ -84,8 +84,8 @@ less-privileged levels, but not at its own level. This is analogous to how the
 existing `counteren` CSRs control access to performance counter registers. Just
 as with the `counteren` CSRs, when a `stateen` CSR prevents access to state by
 less-privileged levels, an attempt in one of those privilege modes to execute
-an instruction that would read or write the protected state raises an illegal
-instruction exception, or, if executing in VS or VU mode and the circumstances
+an instruction that would read or write the protected state raises an illegal-instruction
+exception, or, if executing in VS or VU mode and the circumstances
 for a virtual-instruction  exception apply, raises a virtual-instruction
 exception instead of an illegal-instruction exception.
 

src/v-st-ext.adoc

@@ -539,8 +539,8 @@ The `vstart` CSR is writable by unprivileged code, but non-zero
 `vstart` values may cause vector instructions to run substantially
 slower on some implementations, so `vstart` should not be used by
 application programmers.  A few vector instructions cannot be
-executed with a non-zero `vstart` value and will raise an illegal
-instruction exception as defined below.
+executed with a non-zero `vstart` value and will raise an
+illegal-instruction exception as defined below.
 
 NOTE: Making `vstart` visible to unprivileged code supports user-level
 threading libraries.
@@ -3874,8 +3874,8 @@ copied to the destination (e.g., by explicitly setting `vl`=1 and
 performing a register-register copy).
 
 Traps on vector reduction instructions are always reported with a
-`vstart` of 0.  Vector reduction operations raise an illegal
-instruction exception if `vstart` is non-zero.
+`vstart` of 0.  Vector reduction operations raise an
+illegal-instruction exception if `vstart` is non-zero.
 
 The assembler syntax for a reduction operation is `vredop.vs`, where
 the `.vs` suffix denotes the first operand is a vector register group

src/zawrs.adoc

@@ -94,7 +94,7 @@ and among implementations. In typical implementations this duration should be
 roughly in the range of 10 to 100 times an on-chip cache miss latency or a
 cacheless access to main memory.
 
-`WRS.NTO`, unlike `WFI`, is not specified to cause an illegal instruction
+`WRS.NTO`, unlike `WFI`, is not specified to cause an illegal-instruction
 exception if executed in U-mode when the governing `TW` bit is 0. `WFI` is
 typically not expected to be used in U-mode and on many systems may promptly
 cause an illegal-instruction exception if used at U-mode. Unlike `WFI`,