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Fetch Instruction/Category clarification (riscv#1824)
* Enhance FENCE table * Caps FENCE * Tweak description of FENCE The description of the "FENCE" instructions under "Memory Ordering Instructions" (section 2.7) has some inconsistencies which are magnified by the coexistence of "FENCE" as a set of instructions depending on the value of the _fm_ field, and a specific instruction that uses the `FENCE` mnemonic when _fm_=0b0000. Try to improve the documentation in this section with the following changes: - I avoid "the FENCE instruction" in favor of "FENCE instructions" or "a FENCE instruction" (just all caps here, too). - I capitalized "fence" when it was clearly referring to "FENCE instructions". - I used `FENCE` when the referring to the `FENCE` instruction (with _fm_=0000). - I put "with _fm_=0000" in paretheses when it was already associated with the `FENCE` instruction (with _fm_=0000) to convey that this was just to add some clarity (not specialization) for something that should already be fairly clear. (Although using text attributes for clarity is not terribly accessible, perhaps?) - I changed uses of `FENCE` to FENCE when it was referring to the class. - I put all references to `FENCE.TSO` in backticks, since this is referring to a specific instruction (not the class). - I put all references like `FENCE RW,RW` in backticks, since this is referring to a specific instruction. - In this text: > many _fm_ and predecessor/successor set settings in <<fm>> are also reserved for future use. I removed "in <<fm>>" because I couldn't make sense of that sentence otherwise. - I replaced "normal fences" with "`FENCE` instructions (with _fm_=0000)", since it's really a reference to a specific instruction. --------- Co-authored-by: Paul A. Clarke <[email protected]>
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src/rv32.adoc

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@@ -792,7 +792,7 @@ include::images/wavedrom/mem-order.edn[]
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[[mem-order]]
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//.Memory ordering instructions
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The FENCE instruction is used to order device I/O and memory accesses as
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FENCE instructions are used to order device I/O and memory accesses as
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viewed by other RISC-V harts and external devices or coprocessors. Any
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combination of device input (I), device output (O), memory reads \(R),
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and memory writes (W) may be ordered with respect to any combination of
@@ -802,9 +802,9 @@ any operation in the _predecessor_ set preceding the FENCE.
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<<memorymodel>> provides a precise description
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of the RISC-V memory consistency model.
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The FENCE instruction also orders memory reads and writes made by the
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FENCE instructions also order memory reads and writes made by the
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hart as observed by memory reads and writes made by an external device.
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However, FENCE does not order observations of events made by an external
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However, FENCE instructions do not order observations of events made by an external
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device using any other signaling mechanism.
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[NOTE]
@@ -813,7 +813,7 @@ A device might observe an access to a memory location via some external
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communication mechanism, e.g., a memory-mapped control register that
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drives an interrupt signal to an interrupt controller. This
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communication is outside the scope of the FENCE ordering mechanism and
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hence the FENCE instruction can provide no guarantee on when a change in
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hence FENCE instructions can provide no guarantee on when a change in
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the interrupt signal is visible to the interrupt controller. Specific
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devices might provide additional ordering guarantees to reduce software
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overhead but those are outside the scope of the RISC-V memory model.
@@ -827,23 +827,23 @@ memory-mapped I/O devices will typically be accessed with uncached loads
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and stores that are ordered using the I and O bits rather than the R and
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W bits. Instruction-set extensions might also describe new I/O
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instructions that will also be ordered using the I and O bits in a
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FENCE.
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FENCE instruction.
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[[fm]]
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[float="center",align="center",cols="^1,^1,<3",options="header"]
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.Fence mode encoding
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|===
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|_fm_ field |Mnemonic |Meaning
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|_fm_ field |Mnemonic suffix|Meaning
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|0000 |_none_ |Normal Fence
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|1000 |TSO |With `FENCE RW,RW`: exclude write-to-read ordering; otherwise: _Reserved for future use._
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2+|_other_ |_Reserved for future use._
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|1000 |.TSO |With `FENCE RW,RW`: exclude write-to-read ordering; otherwise: _Reserved for future use._
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|_other_|_other_ |_Reserved for future use._
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|===
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The fence mode field _fm_ defines the semantics of the `FENCE`. A `FENCE`
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with _fm_=`0000` orders all memory operations in its predecessor set
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The FENCE mode field _fm_ defines the semantics of the FENCE instruction. A `FENCE`
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(with _fm_=`0000`) orders all memory operations in its predecessor set
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before all memory operations in its successor set.
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The `FENCE.TSO` instruction is encoded as a `FENCE` instruction
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A `FENCE.TSO` instruction is encoded as a FENCE instruction
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with _fm_=`1000`, _predecessor_=`RW`, and _successor_=`RW`. `FENCE.TSO` orders
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all load operations in its predecessor set before all memory operations
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in its successor set, and all store operations in its predecessor set
@@ -853,17 +853,17 @@ store operations in the `FENCE.TSO's` predecessor set unordered with
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[NOTE]
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====
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Because FENCE RW,RW imposes a superset of the orderings that FENCE.TSO
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imposes, it is correct to ignore the _fm_ field and implement FENCE.TSO as FENCE RW,RW.
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Because `FENCE RW,RW` imposes a superset of the orderings that `FENCE.TSO`
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imposes, it is correct to ignore the _fm_ field and implement `FENCE.TSO` as `FENCE RW,RW`.
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====
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The unused fields in the `FENCE` instructions--_rs1_ and _rd_--are reserved
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The unused fields in the FENCE instructions--_rs1_ and _rd_--are reserved
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for finer-grain fences in future extensions. For forward compatibility,
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base implementations shall ignore these fields, and standard software
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shall zero these fields. Likewise, many _fm_ and predecessor/successor
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set settings in <<fm>> are also reserved for future use.
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set settings are also reserved for future use.
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Base implementations shall treat all such reserved configurations as
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normal fences with _fm_=0000, and standard software shall use only
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`FENCE` instructions (with _fm_=`0000`), and standard software shall use only
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non-reserved configurations.
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[NOTE]
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and also to support alternative non-memory paths to control added
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coprocessors or I/O devices. Simple implementations may additionally
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ignore the _predecessor_ and _successor_ fields and always execute a
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conservative fence on all operations.
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conservative FENCE on all operations.
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====
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[[ecall-ebreak]]

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