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Add XML target descriptions for standard Opella reg files
Signed-off-by: Anton Kolesov <[email protected]>
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‎extras/opella-xd/opella-arc600-tdesc.xml‎

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<?xml version="1.0"?>
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<!-- Copyright 2015 (c) Synopsys Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE target SYSTEM "gdb-target.dtd">
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<target>
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<architecture>arc:ARCv2</architecture>
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<!-- No OSABI for bare metal -->
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<!-- No compatibility for ARC -->
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<feature name="org.gnu.gdb.arc.core.v2">
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<reg name="r0" bitsize="32" group="general"/>
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<reg name="r1" bitsize="32" group="general"/>
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<reg name="r2" bitsize="32" group="general"/>
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<reg name="r3" bitsize="32" group="general"/>
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<reg name="r4" bitsize="32" group="general"/>
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<reg name="r5" bitsize="32" group="general"/>
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<reg name="r6" bitsize="32" group="general"/>
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<reg name="r7" bitsize="32" group="general"/>
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<reg name="r8" bitsize="32" group="general"/>
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<reg name="r9" bitsize="32" group="general"/>
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<reg name="r10" bitsize="32" group="general"/>
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<reg name="r11" bitsize="32" group="general"/>
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<reg name="r12" bitsize="32" group="general"/>
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<reg name="r13" bitsize="32" group="general"/>
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<reg name="r14" bitsize="32" group="general"/>
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<reg name="r15" bitsize="32" group="general"/>
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<reg name="r16" bitsize="32" group="general"/>
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<reg name="r17" bitsize="32" group="general"/>
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<reg name="r18" bitsize="32" group="general"/>
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<reg name="r19" bitsize="32" group="general"/>
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<reg name="r20" bitsize="32" group="general"/>
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<reg name="r21" bitsize="32" group="general"/>
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<reg name="r22" bitsize="32" group="general"/>
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<reg name="r23" bitsize="32" group="general"/>
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<reg name="r24" bitsize="32" group="general"/>
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<reg name="r25" bitsize="32" group="general"/>
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<!-- ARC core pointer registers -->
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<reg name="gp" bitsize="32" group="general" type="data_ptr"/>
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<reg name="fp" bitsize="32" group="general" type="data_ptr"/>
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<reg name="sp" bitsize="32" group="general" type="data_ptr"/>
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<!-- Code pointers. R30 is general purpose, but it used to be ILINK2 in
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ARCompact, thus its odd position in between of special purpose registers.
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GCC does't use this register, so it isn't a member of general group. -->
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<reg name="ilink" bitsize="32" group="general" type="code_ptr"/>
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<reg name="r30" bitsize="32" group=""/>
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<reg name="blink" bitsize="32" group="general" type="code_ptr"/>
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<reg name="lp_count" bitsize="32" group="general" type="uint32" regnum="60"/>
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<reg name="pcl" bitsize="32" group="" type="code_ptr" regnum="63"/>
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</feature>
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<xi:include href="aux-minimal.xml"/>
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<feature name="org.gnu.gdb.arc.aux-other">
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<reg bitsize="32" name="STATUS" group=""/>
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<reg bitsize="32" name="SEMAPHORE" group=""/>
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<reg bitsize="32" name="IDENTITY" group=""/>
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<reg bitsize="32" name="DEBUG" group=""/>
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<reg bitsize="32" name="STATUS32_L1" group=""/>
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<reg bitsize="32" name="STATUS32_L2" group=""/>
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<reg bitsize="32" name="COUNT0" group=""/>
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<reg bitsize="32" name="CONTROL0" group=""/>
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<reg bitsize="32" name="LIMIT0" group=""/>
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<reg bitsize="32" name="INT_VECTOR_BASE" group=""/>
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<reg bitsize="32" name="AUX_MACMODE" group=""/>
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<reg bitsize="32" name="AUX_IRQ_LV12" group=""/>
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<reg bitsize="32" name="COUNT1" group=""/>
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<reg bitsize="32" name="CONTROL1" group=""/>
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<reg bitsize="32" name="LIMIT1" group=""/>
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<reg bitsize="32" name="AUX_IRQ_LEV" group=""/>
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<reg bitsize="32" name="AUX_IRQ_HINT" group=""/>
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<!-- cache control regs -->
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<!-- N.B. are the Invalidation regs write-only? -->
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<reg bitsize="32" name="IC_IVIC" group=""/>
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<reg bitsize="32" name="IC_CTRL" group=""/>
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<reg bitsize="32" name="DC_IVDC" group=""/>
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<reg bitsize="32" name="DC_CTRL" group=""/>
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<!-- actionpoint 0 regs -->
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<reg bitsize="32" name="AMV0" group=""/>
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<reg bitsize="32" name="AMM0" group=""/>
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<reg bitsize="32" name="AC0" group=""/>
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<!-- Build Configuration Registers -->
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="DCCM_BASE_BUILD" group=""/>
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<reg bitsize="32" name="CRC_BASE_BUILD" group=""/>
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<reg bitsize="32" name="DVBF_BUILD" group=""/>
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<reg bitsize="32" name="TEL_INSTR_BUILD" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="MEMSUBSYS" group=""/>
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<reg bitsize="32" name="VECBASE_AC_BUILD" group=""/>
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<reg bitsize="32" name="P_BASE_ADDRESS" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="RF_BUILD" group=""/>
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<reg bitsize="32" name="MMU_BUILD" group=""/>
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<reg bitsize="32" name="ARCANGEL_BUILD" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="DCACHE_BUILD" group=""/>
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<reg bitsize="32" name="MADI_BUILD" group=""/>
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<reg bitsize="32" name="DCCM_BUILD" group=""/>
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<reg bitsize="32" name="TIMER_BUILD" group=""/>
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<reg bitsize="32" name="AP_BUILD" group=""/>
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<reg bitsize="32" name="ICACHE_BUILD" group=""/>
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<reg bitsize="32" name="ICCM_BUILD" group=""/>
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<reg bitsize="32" name="DSPRAM_BUILD" group=""/>
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<reg bitsize="32" name="MAC_BUILD" group=""/>
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<reg bitsize="32" name="MULTIPLY_BUILD" group=""/>
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<reg bitsize="32" name="SWAP_BUILD" group=""/>
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<reg bitsize="32" name="NORM_BUILD" group=""/>
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<reg bitsize="32" name="MINMAX_BUILD" group=""/>
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<reg bitsize="32" name="BARREL_BUILD" group=""/>
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</feature>
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</target>

‎extras/opella-xd/opella-arc700-tdesc.xml‎

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<?xml version="1.0"?>
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<!-- Copyright 2015 (c) Synopsys Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE target SYSTEM "gdb-target.dtd">
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<target>
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<architecture>arc:ARCv2</architecture>
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<!-- No OSABI for bare metal -->
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<!-- No compatibility for ARC -->
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<feature name="org.gnu.gdb.arc.core.v2">
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<reg name="r0" bitsize="32" group="general"/>
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<reg name="r1" bitsize="32" group="general"/>
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<reg name="r2" bitsize="32" group="general"/>
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<reg name="r3" bitsize="32" group="general"/>
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<reg name="r4" bitsize="32" group="general"/>
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<reg name="r5" bitsize="32" group="general"/>
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<reg name="r6" bitsize="32" group="general"/>
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<reg name="r7" bitsize="32" group="general"/>
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<reg name="r8" bitsize="32" group="general"/>
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<reg name="r9" bitsize="32" group="general"/>
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<reg name="r10" bitsize="32" group="general"/>
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<reg name="r11" bitsize="32" group="general"/>
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<reg name="r12" bitsize="32" group="general"/>
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<reg name="r13" bitsize="32" group="general"/>
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<reg name="r14" bitsize="32" group="general"/>
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<reg name="r15" bitsize="32" group="general"/>
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<reg name="r16" bitsize="32" group="general"/>
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<reg name="r17" bitsize="32" group="general"/>
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<reg name="r18" bitsize="32" group="general"/>
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<reg name="r19" bitsize="32" group="general"/>
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<reg name="r20" bitsize="32" group="general"/>
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<reg name="r21" bitsize="32" group="general"/>
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<reg name="r22" bitsize="32" group="general"/>
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<reg name="r23" bitsize="32" group="general"/>
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<reg name="r24" bitsize="32" group="general"/>
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<reg name="r25" bitsize="32" group="general"/>
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<!-- ARC core pointer registers -->
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<reg name="gp" bitsize="32" group="general" type="data_ptr"/>
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<reg name="fp" bitsize="32" group="general" type="data_ptr"/>
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<reg name="sp" bitsize="32" group="general" type="data_ptr"/>
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<!-- Code pointers. R30 is general purpose, but it used to be ILINK2 in
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ARCompact, thus its odd position in between of special purpose registers.
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GCC does't use this register, so it isn't a member of general group. -->
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<reg name="ilink" bitsize="32" group="general" type="code_ptr"/>
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<reg name="r30" bitsize="32" group=""/>
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<reg name="blink" bitsize="32" group="general" type="code_ptr"/>
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<reg name="lp_count" bitsize="32" group="general" type="uint32" regnum="60"/>
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<reg name="pcl" bitsize="32" group="" type="code_ptr" regnum="63"/>
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</feature>
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<xi:include href="aux-minimal.xml"/>
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<feature name="org.gnu.gdb.arc.aux-other">
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<reg bitsize="32" name="STATUS" group=""/>
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<reg bitsize="32" name="IDENTITY" group=""/>
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<reg bitsize="32" name="DEBUG" group=""/>
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<reg bitsize="32" name="STATUS32_L1" group=""/>
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<reg bitsize="32" name="STATUS32_L2" group=""/>
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<reg bitsize="32" name="COUNT0" group=""/>
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<reg bitsize="32" name="CONTROL0" group=""/>
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<reg bitsize="32" name="LIMIT0" group=""/>
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<reg bitsize="32" name="INT_VECTOR_BASE" group=""/>
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<reg bitsize="32" name="AUX_MACMODE" group=""/>
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<reg bitsize="32" name="AUX_IRQ_LV12" group=""/>
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<reg bitsize="32" name="COUNT1" group=""/>
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<reg bitsize="32" name="CONTROL1" group=""/>
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<reg bitsize="32" name="LIMIT1" group=""/>
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<reg bitsize="32" name="AUX_IRQ_LEV" group=""/>
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<reg bitsize="32" name="AUX_IRQ_HINT" group=""/>
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<reg bitsize="32" name="ERET" group=""/>
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<reg bitsize="32" name="ERBTA" group=""/>
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<reg bitsize="32" name="ERSTATUS" group=""/>
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<reg bitsize="32" name="ECR" group=""/>
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<reg bitsize="32" name="EFA" group=""/>
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<reg bitsize="32" name="ICAUSE1" group=""/>
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<reg bitsize="32" name="ICAUSE2" group=""/>
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<reg bitsize="32" name="AUX_IENABLE" group=""/>
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<reg bitsize="32" name="AUX_ITRIGGER" group=""/>
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<reg bitsize="32" name="XPU" group=""/>
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<reg bitsize="32" name="BTA" group=""/>
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<reg bitsize="32" name="BTA_L1" group=""/>
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<reg bitsize="32" name="BTA_L2" group=""/>
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<reg bitsize="32" name="AUX_IRQ_PULSE_CANCEL" group=""/>
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<reg bitsize="32" name="AUX_IRQ_PENDING" group=""/>
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<!-- cache control regs -->
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<reg bitsize="32" name="IC_IVIC" group=""/>
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<reg bitsize="32" name="IC_CTRL" group=""/>
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<reg bitsize="32" name="DC_IVDC" group=""/>
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<reg bitsize="32" name="DC_CTRL" group=""/>
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<!-- actionpoint 0 regs -->
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<reg bitsize="32" name="AMV0" group=""/>
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<reg bitsize="32" name="AMM0" group=""/>
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<reg bitsize="32" name="AC0" group=""/>
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<!-- Build Configuration Registers -->
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="DCCM_BASE_BUILD" group=""/>
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<reg bitsize="32" name="CRC_BASE_BUILD" group=""/>
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<reg bitsize="32" name="BTA_LINK_BUILD" group=""/>
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<reg bitsize="32" name="DVBF_BUILD" group=""/>
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<reg bitsize="32" name="TEL_INSTR_BUILD" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="MEMSUBSYS" group=""/>
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<reg bitsize="32" name="VECBASE_AC_BUILD" group=""/>
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<reg bitsize="32" name="P_BASE_ADDRESS" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="MMU_BUILD" group=""/>
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<reg bitsize="32" name="ARCANGEL_BUILD" group=""/>
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<reg bitsize="32" name="unused" group=""/>
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<reg bitsize="32" name="DCACHE_BUILD" group=""/>
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<reg bitsize="32" name="MADI_BUILD" group=""/>
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<reg bitsize="32" name="DCCM_BUILD" group=""/>
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<reg bitsize="32" name="TIMER_BUILD" group=""/>
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<reg bitsize="32" name="AP_BUILD" group=""/>
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<reg bitsize="32" name="ICACHE_BUILD" group=""/>
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<reg bitsize="32" name="ICCM_BUILD" group=""/>
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<reg bitsize="32" name="DSPRAM_BUILD" group=""/>
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<reg bitsize="32" name="MAC_BUILD" group=""/>
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<reg bitsize="32" name="MULTIPLY_BUILD" group=""/>
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<reg bitsize="32" name="SWAP_BUILD" group=""/>
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<reg bitsize="32" name="NORM_BUILD" group=""/>
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<reg bitsize="32" name="MINMAX_BUILD" group=""/>
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<reg bitsize="32" name="BARREL_BUILD" group=""/>
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</feature>
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</target>

‎extras/opella-xd/opella-arcem-tdesc.xml‎

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<?xml version="1.0"?>
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<!-- Copyright 2015 (c) Synopsys Inc.
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Copying and distribution of this file, with or without modification,
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are permitted in any medium without royalty provided the copyright
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notice and this notice are preserved. -->
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<!DOCTYPE target SYSTEM "gdb-target.dtd">
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<target>
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<architecture>arc:ARCv2</architecture>
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<!-- No OSABI for bare metal -->
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<!-- No compatibility for ARC -->
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<feature name="org.gnu.gdb.arc.core.v2">
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<reg name="r0" bitsize="32" group="general"/>
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<reg name="r1" bitsize="32" group="general"/>
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<reg name="r2" bitsize="32" group="general"/>
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<reg name="r3" bitsize="32" group="general"/>
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<reg name="r4" bitsize="32" group="general"/>
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<reg name="r5" bitsize="32" group="general"/>
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<reg name="r6" bitsize="32" group="general"/>
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<reg name="r7" bitsize="32" group="general"/>
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<reg name="r8" bitsize="32" group="general"/>
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<reg name="r9" bitsize="32" group="general"/>
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<reg name="r10" bitsize="32" group="general"/>
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<reg name="r11" bitsize="32" group="general"/>
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<reg name="r12" bitsize="32" group="general"/>
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<reg name="r13" bitsize="32" group="general"/>
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<reg name="r14" bitsize="32" group="general"/>
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<reg name="r15" bitsize="32" group="general"/>
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<reg name="r16" bitsize="32" group="general"/>
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<reg name="r17" bitsize="32" group="general"/>
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<reg name="r18" bitsize="32" group="general"/>
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<reg name="r19" bitsize="32" group="general"/>
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<reg name="r20" bitsize="32" group="general"/>
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<reg name="r21" bitsize="32" group="general"/>
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<reg name="r22" bitsize="32" group="general"/>
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<reg name="r23" bitsize="32" group="general"/>
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<reg name="r24" bitsize="32" group="general"/>
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<reg name="r25" bitsize="32" group="general"/>
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<!-- ARC core pointer registers -->
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<reg name="gp" bitsize="32" group="general" type="data_ptr"/>
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<reg name="fp" bitsize="32" group="general" type="data_ptr"/>
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<reg name="sp" bitsize="32" group="general" type="data_ptr"/>
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<!-- Code pointers. R30 is general purpose, but it used to be ILINK2 in
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ARCompact, thus its odd position in between of special purpose registers.
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GCC does't use this register, so it isn't a member of general group. -->
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<reg name="ilink" bitsize="32" group="general" type="code_ptr"/>
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<reg name="r30" bitsize="32" group=""/>
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<reg name="blink" bitsize="32" group="general" type="code_ptr"/>
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<reg name="lp_count" bitsize="32" group="general" type="uint32" regnum="60"/>
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<reg name="pcl" bitsize="32" group="" type="code_ptr" regnum="63"/>
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</feature>
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<xi:include href="aux-minimal.xml"/>
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<feature name="org.gnu.gdb.arc.aux-other">
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<reg bitsize="32" name="IDENTITY" group=""/>
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<reg bitsize="32" name="BTA" group=""/>
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<reg bitsize="32" name="ECR" group=""/>
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<reg bitsize="32" name="INT_VECTOR_BASE" group=""/>
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<!-- baseline: exception and interruipt state -->
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<reg bitsize="32" name="ERET" group=""/>
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<reg bitsize="32" name="ERBTA" group=""/>
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<reg bitsize="32" name="ERSTATUS" group=""/>
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<!-- code density -->
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<reg bitsize="32" name="JLI_BASE" group=""/>
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<reg bitsize="32" name="LDI_BASE" group=""/>
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<reg bitsize="32" name="EI_BASE" group=""/>
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<!-- debug feature -->
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<reg bitsize="32" name="DEBUG" group=""/>
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<reg bitsize="32" name="DEBUGI" group=""/>
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<!-- Timer 0 -->
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<reg bitsize="32" name="COUNT0" group=""/>
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<reg bitsize="32" name="CONTROL0" group=""/>
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<reg bitsize="32" name="LIMIT0" group=""/>
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<!-- Timer 1 -->
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<reg bitsize="32" name="COUNT1" group=""/>
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<reg bitsize="32" name="CONTROL1" group=""/>
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<reg bitsize="32" name="LIMIT1" group=""/>
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<!-- caches are not present in em4. might make sense for EM6 though -->
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<reg bitsize="32" name="IC_IVIC" group=""/>
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<reg bitsize="32" name="IC_CTRL" group=""/>
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<reg bitsize="32" name="IC_LIL" group=""/>
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<reg bitsize="32" name="IC_IVIL" group=""/>
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<reg bitsize="32" name="IC_RAM_ADDR" group=""/>
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<reg bitsize="32" name="IC_TAG" group=""/>
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<reg bitsize="32" name="IC_DATA" group=""/>
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<reg bitsize="32" name="DC_IVDC" group=""/>
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<reg bitsize="32" name="DC_CTRL" group=""/>
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<reg bitsize="32" name="DC_FLSH" group=""/>
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<reg bitsize="32" name="AUX_CACHE_LIMIT" group=""/>
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<reg bitsize="32" name="DC_LDL" group=""/>
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<reg bitsize="32" name="DC_IVDL" group=""/>
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<reg bitsize="32" name="DC_FLDL" group=""/>
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<reg bitsize="32" name="DC_RAM_ADDR" group=""/>
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<reg bitsize="32" name="DC_TAG" group=""/>
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<reg bitsize="32" name="DC_DATA" group=""/>
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<reg bitsize="32" name="AUX_ICCM" group=""/>
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<reg bitsize="32" name="AUX_DCCM" group=""/>
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<reg bitsize="32" name="SMART_CONTROL" group=""/>
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<reg bitsize="32" name="SMART_DATA" group=""/>
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<reg bitsize="32" name="AUX_IRQ_CTRL" group=""/>
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<reg bitsize="32" name="IRQ_PRIORITY_PENDING" group=""/>
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<reg bitsize="32" name="AUX_IRQ_ACT" group=""/>
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<reg bitsize="32" name="IRQ_SELECT" group=""/>
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<reg bitsize="32" name="IRQ_PRIORITY" group=""/>
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<reg bitsize="32" name="IRQ_ENABLE" group=""/>
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<reg bitsize="32" name="IRQ_TRIGGER" group=""/>
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<reg bitsize="32" name="IRQ_PENDING" group=""/>
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<reg bitsize="32" name="IRQ_PULSE_CANCEL" group=""/>
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<reg bitsize="32" name="IRQ_STATUS" group=""/>
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<reg bitsize="32" name="AUX_IRQ_HINT" group=""/>
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<reg bitsize="32" name="ICAUSE" group=""/>
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<!-- no stack checking in EM Starter Kit -->
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<reg bitsize="32" name="AUX_USER_SP" group=""/>
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<reg bitsize="32" name="AMV0" group=""/>
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<reg bitsize="32" name="AMM0" group=""/>
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<reg bitsize="32" name="AC0" group=""/>
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<!-- Build Configuration Registers -->
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<!-- BCR:baseline -->
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<reg bitsize="32" name="BCR_VER" group=""/>
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<reg bitsize="32" name="BTA_LINK_BUILD" group=""/>
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<reg bitsize="32" name="VECBASE_AC_BUILD" group=""/>
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<reg bitsize="32" name="RF_BUILD" group=""/>
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<reg bitsize="32" name="ISA_CONFIG" group=""/>
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<reg bitsize="32" name="D_CACHE_BUILD" group=""/>
137+
<reg bitsize="32" name="DCCM_BUILD" group=""/>
138+
<reg bitsize="32" name="SMART_BUILD" group=""/>
139+
<reg bitsize="32" name="TIMER_BUILD" group=""/>
140+
<reg bitsize="32" name="AP_BUILD" group=""/>
141+
<reg bitsize="32" name="I_CACHE_BUILD" group=""/>
142+
<reg bitsize="32" name="ICCM_BUILD" group=""/>
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<reg bitsize="32" name="MULTIPLY_BUILD" group=""/>
144+
<reg bitsize="32" name="SWAP_BUILD" group=""/>
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<reg bitsize="32" name="NORM_BUILD" group=""/>
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<reg bitsize="32" name="MINMAX_BUILD" group=""/>
147+
<reg bitsize="32" name="BARREL_BUILD" group=""/>
148+
<reg bitsize="32" name="IRQ_BUILD" group=""/>
149+
</feature>
150+
</target>

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