ARC objdump has wrong register representation (rNrN+1 instead of rN only)

[kopartm]

ARC objdump (architecture: arc64:64) generates code with r2r3 register representation:
format elf64-littlearc64

 812:	1000 0682           	lddl	r2r3,[r0]
 816:	1c00 30a6           	stdl	r2r3,[sp,0]
 81a:	1000 0682           	lddl	r2r3,[r0]

It's not possible to use this code in an assembler directly due to the incorrect "rNrN+1" register format:
app.cc:32: error: unknown register name 'r2r3' in 'asm'
app.cc:32: error: unknown register name 'r0r1' in 'asm'

The assembler code is with one register only (r0 or r2 only).
This inconsistency should be fixed.

[kolerov]

Hi @kopartm,

What toolchain version do you use? And what is your exact command line for this issue? I see that I can use this format in arc-2024.06 release:

$ arc64-snps-elf-as --version
GNU assembler (ARCv3 elf toolchain - build 7032) 2.42.0.20240522
Copyright (C) 2024 Free Software Foundation, Inc.
This program is free software; you may redistribute it under the terms of
the GNU General Public License version 3 or later.
This program has absolutely no warranty.
This assembler was configured for a target of `arc64-snps-elf'.

$ cat test.s 
lddl r0,   [r0]
stdl r2,   [sp,0]
lddl r2r3, [r0]
stdl r2r3, [sp,0]
lddl r2r3, [r0]

$ arc64-snps-elf-as -mcpu=hs68 test.s -o test.o
$ arc64-snps-elf-objdump -d test.o

test.o:     file format elf64-littlearc64


Disassembly of section .text:

0000000000000000 <.text>:
   0:   1000 0680               lddl    r0r1,[r0]
   4:   1c00 30a6               stdl    r2r3,[sp,0]
   8:   1000 0682               lddl    r2r3,[r0]
   c:   1c00 30a6               stdl    r2r3,[sp,0]
  10:   1000 0682               lddl    r2r3,[r0]

[kopartm]

You have just duplicated the same bug in your comment.
Your disassembler/dump:
0: 1000 0680 lddl r0r1,[r0]

The r0r1 is not correct if you want to use it as is in your assembler source.

[kolerov]

@kopartm in my example I constructed a .s file with instructions that use rNrN+1 format and compiled it successfully. On my side this example works with r0r1 too and with any legal rNrN+1 pair. Could you provide us with your setup and commands?