Skip to content

Commit 676bdaa

Browse files
author
Siyuan Cheng
committed
arc: add nsim_em11d target
add nsim_em11d target specific for DSP feature Signed-off-by: Siyuan Cheng <[email protected]>
1 parent 4203376 commit 676bdaa

File tree

10 files changed

+277
-0
lines changed

10 files changed

+277
-0
lines changed

‎boards/arc/nsim/doc/index.rst‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -18,13 +18,15 @@ There are four supported board sub-configurations:
1818

1919
* ``nsim_em`` which includes normal ARC EM features and ARC MPUv2
2020
* ``nsim_em_em7d_v22`` which includes normal ARC EM features and ARC MPUv2, specially with one register bank and fast irq
21+
* ``nsim_em_em11d`` which includes normal ARC EM features and ARC MPUv2, specially with XY memory and DSP feature.
2122
* ``nsim_sem`` which includes secure ARC EM features and ARC MPUv3
2223
* ``nsim_hs`` which includes base ARC HS features, i.e. w/o PMU and MMU
2324
* ``nsim_hs_smp`` which includes base ARC HS features in multi-core cluster, still w/o PMU and MMU
2425

2526
For detailed arc features, please refer to
2627
:zephyr_file:`boards/arc/nsim/support/nsim_em.props`,
2728
:zephyr_file:`boards/arc/nsim/support/nsim_em7d_v22.props`,
29+
:zephyr_file:`boards/arc/nsim/support/nsim_em11d.props`,
2830
:zephyr_file:`boards/arc/nsim/support/nsim_sem.props`,
2931
:zephyr_file:`boards/arc/nsim/support/nsim_hs.props` and
3032
:zephyr_file:`boards/arc/nsim/support/mdb_hs_smp.args`

‎boards/arc/nsim/nsim_em11d.dts‎

Lines changed: 33 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,33 @@
1+
/*
2+
* Copyright (c) 2022 Synopsys, Inc. All rights reserved.
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
6+
7+
/dts-v1/;
8+
9+
#include "nsim_em.dtsi"
10+
11+
#define XCCM_ADDR c0000000
12+
#define XCCM_SIZE DT_SIZE_K(64)
13+
#define YCCM_ADDR e0000000
14+
#define YCCM_SIZE DT_SIZE_K(64)
15+
16+
/ {
17+
model = "snps,nsim_em";
18+
compatible = "snps,nsim_em";
19+
20+
xccm0: xccm@XCCM_ADDR {
21+
compatible = "arc,xccm";
22+
reg = <DT_ADDR(XCCM_ADDR) XCCM_SIZE>;
23+
};
24+
25+
yccm0: yccm@YCCM_ADDR {
26+
compatible = "arc,yccm";
27+
reg = <DT_ADDR(YCCM_ADDR) YCCM_SIZE>;
28+
};
29+
};
30+
31+
&cpu0 {
32+
clock-frequency = <5000000>;
33+
};

‎boards/arc/nsim/nsim_em11d.yaml‎

Lines changed: 11 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,11 @@
1+
identifier: nsim_em11d
2+
name: EM11D Nsim simulator
3+
type: mcu
4+
simulation: nsim
5+
arch: arc
6+
toolchain:
7+
- arcmwdt
8+
testing:
9+
ignore_tags:
10+
- net
11+
- bluetooth

‎boards/arc/nsim/nsim_em11d_defconfig‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,16 @@
1+
# SPDX-License-Identifier: Apache-2.0
2+
3+
CONFIG_SOC_NSIM=y
4+
CONFIG_SOC_NSIM_EM11D=y
5+
CONFIG_BOARD_NSIM=y
6+
CONFIG_SYS_CLOCK_TICKS_PER_SEC=100
7+
CONFIG_XIP=n
8+
CONFIG_BUILD_OUTPUT_BIN=n
9+
CONFIG_ARCV2_INTERRUPT_UNIT=y
10+
CONFIG_ARCV2_TIMER=y
11+
CONFIG_ARC_MPU_ENABLE=y
12+
CONFIG_CONSOLE=y
13+
CONFIG_UART_CONSOLE=y
14+
CONFIG_SERIAL=y
15+
CONFIG_ARC_EXCEPTION_DEBUG=y
16+
CONFIG_ARC_USE_UNALIGNED_MEM_ACCESS=y

‎boards/arc/nsim/support/mdb_em11d.args‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
1+
-arcv2em
2+
-core3
3+
-rgf_num_banks=2
4+
-rgf_banked_regs=32
5+
-rgf_num_wr_ports=2
6+
-Xcode_density
7+
-Xdiv_rem=radix2
8+
-turbo_boost
9+
-Xswap
10+
-Xbitscan
11+
-Xmpy_option=mpyd
12+
-mpu
13+
-mpu_regions=16
14+
-Xshift_assist
15+
-Xbarrel_shifter
16+
-Xdsp2
17+
-Xdsp_complex
18+
-Xdsp_divsqrt=radix2
19+
-Xdsp_itu
20+
-Xdsp_accshift=full
21+
-Xagu_large
22+
-Xagu_wb_depth=4
23+
-Xagu_accord
24+
-Xxy
25+
-Xxy_config=dccm_x_y
26+
-Xxy_size=64K
27+
-Xxy_interleave
28+
-Xxy_x_base=0xc0000000
29+
-Xxy_y_base=0xe0000000
30+
-Xfpus_div
31+
-Xfpu_mac
32+
-Xfpuda
33+
-Xfpus_mpy_slow
34+
-Xfpus_div_slow
35+
-Xtimer0
36+
-Xtimer0_level=1
37+
-Xtimer1
38+
-Xtimer1_level=0
39+
-action_points=2
40+
-Xstack_check
41+
-dmp_peripheral
42+
-smart_stack_entries=8
43+
-interrupts=20
44+
-interrupt_priorities=4
45+
-ext_interrupts=16
46+
-firq
47+
-interrupt_base=0x0
48+
-dcache=16384,32,2,a
49+
-dcache_feature=2
50+
-icache=16384,32,2,a
51+
-icache_feature=2
52+
-dccm_size=0x100000
53+
-dccm_base=0x80000000
54+
-dccm_interleave
55+
-iccm0_size=0x100000
56+
-iccm0_base=0x00000000
57+
-Xpct_counters=8
58+
-dmac
59+
-dmac_channels=2
60+
-dmac_registers=0
61+
-dmac_fifo_depth=2
62+
-dmac_int_config=single_internal
63+
-prop=nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
64+
-noprofile
65+
-Xunaligned

‎boards/arc/nsim/support/nsim_em11d.props‎

Lines changed: 71 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,71 @@
1+
nsim_isa_family=av2em
2+
nsim_isa_core=3
3+
arcver=0x3
4+
nsim_isa_rgf_num_banks=2
5+
nsim_isa_rgf_banked_regs=32
6+
nsim_isa_rgf_num_regs=32
7+
nsim_isa_rgf_num_wr_ports=2
8+
nsim_isa_big_endian=0
9+
nsim_isa_lpc_size=32
10+
nsim_isa_pc_size=32
11+
nsim_isa_addr_size=32
12+
nsim_isa_code_density_option=2
13+
nsim_isa_div_rem_option=1
14+
nsim_isa_turbo_boost=1
15+
nsim_isa_swap_option=1
16+
nsim_isa_bitscan_option=1
17+
nsim_isa_mpy_option=8
18+
nsim_isa_shift_option=3
19+
mpu_regions=16
20+
mpu_version=2
21+
nsim_isa_dsp_option=2
22+
nsim_isa_dsp_complex_option=1
23+
nsim_isa_dsp_divsqrt_option=1
24+
nsim_isa_dsp_itu_option=1
25+
nsim_isa_dsp_itu_option=1
26+
nsim_isa_dsp_accshift_option=2
27+
nsim_isa_agu_size=large
28+
nsim_isa_agu_wb_depth=4
29+
nsim_isa_agu_accord=1
30+
nsim_isa_xy=1
31+
nsim_isa_xy_config=dccm_x_y
32+
nsim_isa_xy_size=64K
33+
nsim_isa_xy_interleave=1
34+
nsim_isa_xy_x_base=0xc0000000
35+
nsim_isa_xy_y_base=0xe0000000
36+
nsim_isa_fpus_div_option=1
37+
nsim_isa_fpu_mac_option=1
38+
nsim_isa_fpuda_option=1
39+
nsim_isa_fpu_fast_mpy_option=0
40+
nsim_isa_fpu_fast_div_option=0
41+
nsim_isa_bitstream_option=1
42+
nsim_isa_enable_timer_0=1
43+
nsim_isa_timer_0_int_level=1
44+
nsim_isa_enable_timer_1=1
45+
nsim_isa_timer_1_int_level=0
46+
nsim_isa_num_actionpoints=2
47+
nsim_isa_stack_checking=1
48+
nsim_isa_has_dmp_peripheral=1
49+
nsim_isa_smart_stack_entries=8
50+
nsim_isa_number_of_interrupts=20
51+
nsim_isa_number_of_levels=4
52+
nsim_isa_number_of_external_interrupts=16
53+
nsim_isa_fast_irq=1
54+
nsim_isa_intvbase_preset=0x0
55+
dcache=16384,32,2,a
56+
nsim_isa_dc_feature_level=2
57+
icache=16384,32,2,a
58+
nsim_isa_ic_feature_level=2
59+
dccm_size=0x100000
60+
dccm_base=0x80000000
61+
nsim_isa_dccm_interleave=1
62+
iccm0_size=0x100000
63+
iccm0_base=0x00000000
64+
nsim_isa_pct_counters=8
65+
nsim_isa_dmac_option=1
66+
nsim_isa_dmac_channels=2
67+
nsim_isa_dmac_registers=0
68+
nsim_isa_dmac_fifo_depth=2
69+
nsim_isa_dmac_int_config=single_internal
70+
nsim_mem-dev=uart0,kind=dwuart,base=0xf0000000,irq=24
71+
nsim_isa_unaligned_option=1

‎soc/arc/snps_nsim/CMakeLists.txt‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -23,6 +23,14 @@ else()
2323
-Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
2424
-Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
2525

26+
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_EM11D -arcv2em -core3 -Xdiv_rem=radix2
27+
-Xmpy_option=mpyd -Xbitscan -Xswap -Xbarrel_shifter
28+
-Xshift_assist -Xdsp2 -Xdsp_complex -Xxy -Xagu_large
29+
-Xdsp_ctrl=postshift,noguard,convergent -Hfxapi
30+
-Xdsp_divsqrt=radix2 -Xdsp_itu -Xdsp_accshift=full
31+
-Xfpus_div -Xfpu_mac -Xfpuda -Xfpus_mpy_slow
32+
-Xfpus_div_slow -Xbitstream -Xtimer0 -Xtimer1)
33+
2634
zephyr_compile_options_ifdef(CONFIG_SOC_NSIM_SEM -arcv2em -core3 -Xcode_density
2735
-Xdiv_rem=radix2 -Xswap -Xbitscan -Xmpy_option=mpyd
2836
-Xshift_assist -Xbarrel_shifter -Xdsp2

‎soc/arc/snps_nsim/Kconfig‎

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,11 @@ config SOC_NSIM_EM7D_V22
1515
select CPU_HAS_MPU
1616
select CPU_HAS_FPU
1717

18+
config SOC_NSIM_EM11D
19+
bool "Synopsys ARC EM11D in nSIM"
20+
select CPU_HAS_MPU
21+
select CPU_HAS_DSP
22+
1823
config SOC_NSIM_SEM
1924
bool "Synopsys ARC SEM in nSIM"
2025
select CPU_HAS_MPU

‎soc/arc/snps_nsim/Kconfig.defconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ config XIP
1010
default n
1111

1212
source "soc/arc/snps_nsim/Kconfig.defconfig.em"
13+
source "soc/arc/snps_nsim/Kconfig.defconfig.em11d"
1314
source "soc/arc/snps_nsim/Kconfig.defconfig.em7d_v22"
1415
source "soc/arc/snps_nsim/Kconfig.defconfig.sem"
1516
source "soc/arc/snps_nsim/Kconfig.defconfig.hs"

‎soc/arc/snps_nsim/Kconfig.defconfig.em11d‎

Lines changed: 65 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,65 @@
1+
# Copyright (c) 2022 Synopsys, Inc. All rights reserved.
2+
# SPDX-License-Identifier: Apache-2.0
3+
4+
if SOC_NSIM_EM11D
5+
6+
config CPU_EM6
7+
default y
8+
9+
config NUM_IRQ_PRIO_LEVELS
10+
# This processor supports 4 priority levels:
11+
# 0 for Fast Interrupts (FIRQs) and 1-3 for Regular Interrupts (IRQs).
12+
default 4
13+
14+
config NUM_IRQS
15+
# must be > the highest interrupt number used
16+
default 30
17+
18+
config ARC_MPU_VER
19+
default 2
20+
21+
config RGF_NUM_BANKS
22+
default 2
23+
24+
config SYS_CLOCK_HW_CYCLES_PER_SEC
25+
default 5000000
26+
27+
config HARVARD
28+
default y
29+
30+
config ARC_FIRQ
31+
default y
32+
33+
config CACHE_MANAGEMENT
34+
default y
35+
36+
config FP_FPU_DA
37+
default y
38+
39+
if (ARC_MPU_VER = 2)
40+
41+
config MAIN_STACK_SIZE
42+
default 2048
43+
44+
config IDLE_STACK_SIZE
45+
default 2048
46+
47+
config ZTEST_STACK_SIZE
48+
default 2048
49+
depends on ZTEST
50+
51+
endif # ARC_MPU_VER
52+
53+
config ARC_HAS_ACCL_REGS
54+
default y
55+
56+
config ARC_HAS_AGU_REGS
57+
default y
58+
59+
config AGU_SHARING
60+
default y
61+
62+
config ARC_AGU_LARGE
63+
default y
64+
65+
endif # SOC_NSIM_EM11D

0 commit comments

Comments
 (0)