boards: snps: nsim: arc_v: add RHX100 board configuration

Add board configuration for RHX100 RISC-V processor.
Provides device tree files for RHX100 and RHX1xx series,
YAML configuration for nSIM simulator integration,
and board-specific default configuration.

Signed-off-by: Afonso Oliveira <[email protected]>

Author: AFOliveira

boards/snps/nsim/arc_v/Kconfig.defconfig

@@ -10,3 +10,10 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 5000000
 
 endif # BOARD_NSIM_ARC_V_RMX100
+
+if BOARD_NSIM_ARC_V_RHX100
+
+config SYS_CLOCK_TICKS_PER_SEC
+	default 10000
+
+endif # BOARD_NSIM_ARC_V_RHX100

boards/snps/nsim/arc_v/Kconfig.nsim_arc_v

@@ -3,3 +3,4 @@
 
 config BOARD_NSIM_ARC_V
 	select SOC_NSIM_ARC_V_RMX100 if BOARD_NSIM_ARC_V_RMX100
+	select SOC_NSIM_ARC_V_RHX100 if BOARD_NSIM_ARC_V_RHX100

boards/snps/nsim/arc_v/board.yml

@@ -4,3 +4,4 @@ board:
   vendor: snps
   socs:
   - name: rmx100
+  - name: rhx100

boards/snps/nsim/arc_v/nsim_arc_v_rhx100.dts

@@ -0,0 +1,23 @@
+/dts-v1/;
+
+#include "rhx100.dtsi"
+
+/ {
+	model = "Synopsys RHX100";
+	compatible = "snps,rhx100";
+
+	aliases {
+		uart-0 = &uart0;
+	};
+
+	chosen {
+		zephyr,sram = &ddr0;
+		zephyr,console = &uart0;
+		zephyr,shell-uart = &uart0;
+	};
+};
+
+&uart0 {
+	status = "okay";
+	current-speed = <115200>;
+};

boards/snps/nsim/arc_v/nsim_arc_v_rhx100.yaml

@@ -0,0 +1,16 @@
+identifier: nsim_arc_v/rhx100
+name: Synopsys rhx100
+simulation:
+  - name: nsim
+    exec: nsimdrv
+type: sim
+arch: riscv
+toolchain:
+  - zephyr
+  - cross-compile
+  - arcmwdt
+testing:
+  ignore_tags:
+    - net
+    - bluetooth
+vendor: snps

boards/snps/nsim/arc_v/nsim_arc_v_rhx100_defconfig

@@ -0,0 +1,10 @@
+# Copyright (c) 2024 Synopsys, Inc.
+# SPDX-License-Identifier: Apache-2.0
+
+CONFIG_XIP=n
+CONFIG_CONSOLE=y
+CONFIG_SERIAL=y
+CONFIG_UART_CONSOLE=y
+CONFIG_BUILD_OUTPUT_HEX=y
+CONFIG_INCLUDE_RESET_VECTOR=y
+CONFIG_LOG=y

boards/snps/nsim/arc_v/rhx100.dtsi

@@ -0,0 +1,8 @@
+#include "rhx1xx.dtsi"
+
+/ {
+	ddr0: memory@80000000  {
+		device_type = "memory";
+		reg = <0x80000000 0x10000000>; /* 256 MB */
+	};
+};

boards/snps/nsim/arc_v/rhx1xx.dtsi

@@ -0,0 +1,62 @@
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+
+	cpus {
+		timebase-frequency = <5000000>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			compatible = "snps,av5rhx", "riscv";
+			device_type = "cpu";
+			reg = <0>;
+			clock-frequency = <5000000>;
+			riscv,isa = "rv32imac_zicsr_zifencei_zba_zbb_zbc_zbs";
+
+			cpu0_intc: interrupt-controller {
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <1>;
+			};
+		};
+	};
+
+	soc {
+		compatible = "simple-bus";
+		ranges;
+		interrupt-parent = <&clint>;
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		clint: clint@a0010000 {
+			compatible = "sifive,clint0";
+			reg = <0xa0010000 0x1000>;
+			interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7>;
+			interrupt-names = "soft0", "timer0";
+		};
+
+		mtimer: timer@a001bff8 {
+			compatible = "riscv,machine-timer";
+			interrupts-extended = <&cpu0_intc 7>;
+			reg = <0xa001bff8 0x8 0xa0014000 0x8>;
+			reg-names = "mtime", "mtimecmp";
+		};
+
+		uart0: serial@10000000{
+			compatible = "ns16550", "snps,dw-apb-uart";
+			reg = <0x10000000 0x400>;
+			reg-shift = <2>;
+
+			/* AIA interrupt controller is not currently implemented,
+			 * so connect UART interrupt to 17th line as a stub to
+			 * make build system and test framework happy.
+			 */
+			interrupt-parent = <&cpu0_intc>;
+			interrupts = <17>;
+			clock-frequency = <50000000>;
+			status = "disabled";
+		};
+	};
+};

boards/snps/nsim/arc_v/support/rhx100.props

@@ -0,0 +1,6 @@
+	nsim_isa_family=rv32
+	nsim_isa_ext=-all.i.m.a.c.s.u.h.zicsr.zifencei.zihintpause.zca.zcb.zcmp.zcmt.zba.zbb.zbc.zbs.zicond.zicbom.zicbop
+	nsim_isa_big_endian=0
+	nsim_mmio_base=2560
+	nsim_mem-dev=uart0,kind=16550,base=0x10000000,irq=24
+	nsim_mem-interface=ARCV_PMP,num_regions=16,granule=1