ORConf 2025 first set of talks

Author: imphil

content/orconf/2025/0.index.md

@@ -28,7 +28,7 @@ The ORConf conference is a weekend of presentations and networking dedicated to
 ::ff-supporting-content
 ## ORConf, the sunshine edition
 
-The FOSSi Foundation is proud to announce the 11th installment of ORConf, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 12 to Sunday September 14 in [Valencia, Spain](https://maps.app.goo.gl/xnXXgU51NMEQn4iK6).
+The FOSSi Foundation is proud to announce the 11th installment of ORConf, a conference dedicated to free and open source silicon to be held over the weekend of Friday September 12 to Sunday September 14 in [Valencia, Spain](#venue).
 
 ORConf is a weekend of presentations and networking for the open source silicon community. Browse through previous installments of ORConf [here](https://fossi-foundation.org/events/archive).
 
@@ -57,13 +57,14 @@ Questions? Ping the organizers via email at [orconf@fossi-foundation.org](mailto
 
   Presentations are submitted through :FfEventbriteLink{:eventId=eventbriteEventId text="the Eventbrite registration interface"}.
 
+  **Talk submissions close on August 24, 2025.**
   Please make your submissions as early as you can, as the presentation slots are likely to fill up quickly.
 
   We aim to give as many people as possible the opportunity to present their exciting work on free and open source silicon.
   To accomodate for that we will determine the duration of a full talk once all submissions are in.
   Historically, full talks ran for 10 minutes (plus time for questions).
   Lightning talks will be 3 minutes.
-  The exact amount of time you'll get will be communicated on acceptance of your talk.
+  The exact amount of time you'll get will be communicated closer to the conference.
 
   ## Code of conduct
 
@@ -87,3 +88,54 @@ Questions? Ping the organizers via email at [orconf@fossi-foundation.org](mailto
   ORConf is organized by volunteers on behalf of the FOSSi Foundation. We are currently looking for more people to help out with arrangements and putting on the event, so please do [email us](mailto:orconf@fossi-foundation.org?subject=Volunteering) if you would like to volunteer for during the event with setup, AV, or even just local knowledge so we can plan the weekend better.
   ::
 ::
+
+## Talks (preliminary)
+
+Talks are published regularly as they are submitted.
+Check this page regularly for updates (or submit your own talk today)!
+
+::ff-event-talks-overview{csvfile="/orconf/2025/talks" view="details"}
+::
+
+## Schedule
+
+The conference will run over three days, Friday, September 12 to Sunday, September 14, 2025.
+We plan to start on Friday morning at 9am and end the conference on Sunday afternoon.
+When planning travel, we suggest you arrive Thursday evening or first thing Friday, and plan to leave Sunday afternoon or evening.
+
+A conference social event will be arranged for Saturday evening.
+
+The detailed schedule of presentations will be available once we have all of the presentation submissions.
+All times are subject to change once we get closer to the event.
+
+### Friday: Conference
+
+Conference from around 9am - 6pm.
+
+### Saturday: Conference, lighning talks, and social event
+
+Conference from around 9am to 6pm, followed by the social event.
+
+### Sunday: Unconference and workshops
+
+On Sunday we will have an unconference and workshops to have more time for focused discussions.
+Even though the exact schedule and topics to talk about will be created together at the event, you can expect in-depth discussions with key stakeholders in Free and Open Source Silicon Projects, demo sessions, hackathrons, and more.
+
+Already booked for this year in a discussion round on sustainability and long-levity of results (tools, IP, etc.) coming out of publicly funded projects.
+
+For exampe, at last year's ORConf we had fantastic sessions on
+* cocotb
+* EU Roadmap
+* Amaranth
+* Open Source DFT and in-field debug
+* Clash and Haskell
+* Surfer
+
+What deep-dives will we have at ORConf?
+It's up to all of us!
+
+## Venue
+
+ORConf 2025 will be held at in Valencia, Spain at the School of Informatics (ETSINF) of the Universitat Politècnica de València.
+
+Address: ETS de Ingeniería Informática, Camí de Vera, s/n, Algirós, 46022 València, Valencia, Spanien ([Google Maps](https://www.google.com/maps/place/UPV+-+ETS+Enginyeria+Inform%C3%A0tica+(ETSINF)/@39.482437,-0.346845,16z/data=!3m1!5s0xd60489ccfe58927:0x9e05d6ff2519e37b!4m6!3m5!1s0xd604883326cd6c7:0xded925519ef13eaf!8m2!3d39.482437!4d-0.346845!16s%2Fg%2F11c1qy0y7k?entry=ttu&g_ep=EgoyMDI1MDcwOS4wIKXMDSoASAFQAw%3D%3D), [OpenStreetMap](https://www.openstreetmap.org/?mlat=39.482388&mlon=-0.346922#map=19/39.482388/-0.346922)).

content/orconf/2025/talks.csv

@@ -0,0 +1,37 @@
+Day,Time,Type,Title,Presenter,Notes,Abstract,Youtube,Slides
+Fri,9:30,Break,Doors open! Register and mingle.,,,,,
+,,Break,Opening,FOSSi Foundation team,,,,
+,,Normal,Guix for FPGAs,Cayetano Santos,,"A new approach in digital electronics design for FPGAs has recently arisen, featuring advanced packaging, versioning and dependency management capabilities for gateware HDL design. Strongly based on Guix dependency manager, this approach departs from traditional methods and opens the door to a fully declarative paradigm on dependency handling, including transactions and determinism, which guarantees traceability during the full design cycle. It is thus possible to treat IP Blocks as any other project requirement -including software-, in addition to producing fully reproducible environments and container images, facilitating the path towards modern continuous integration practices. User custom dedicated repositories allow the development of all that’s necessary to build (hdlmake), simulate (ghdl), and synthesize (yosys) designs remotely, using unit testing frameworks (vunit) and modern verification libraries (osvvm), in addition to performing cosimulation (cocotb) in remote forges.",,
+,,Normal,"GDSFactory: Open-Source EDA for Accelerating Photonics, Quantum, MEMS, and RF Chip Design",Joaquin Matres,,"The design of advanced chips—especially in photonics, quantum, MEMS, and RF—faces critical challenges due to rigid, outdated EDA tools. Many teams resort to custom Python, C, or MATLAB solutions, which offer flexibility but lack scalability. To bridge this gap, we created GDSFactory, an open-source, python-based Analog Electronic Design Automation software that has been downloaded over 2 million times and adopted by companies, universities, and research organizations worldwide.",,
+,,Normal,"Tiliqua - Accessible, Reconfigurable Audio DSP Platform",Sebastian Holzapfel,,"[Tiliqua](https://github.com/apfelaudio/tiliqua) is an open hardware development platform, DSP library and collection of examples (built in Amaranth HDL) that aims to make FPGA-based audio and video synthesis more accessible. This talk builds on [last year's edition](https://fossi-foundation.org/orconf/2024#synthesizing-music-synthesizers), this time covering some war stories from the past 12 months of getting Tiliqua hardware ready to ship, and all the new features added to the DSP/RTL library since then. We'll cover some fun topics such:
+
+* Implementing low-latency USB host purely in gateware
+* Dynamic frequency scaling for display switching
+* New DSP cores and example projects
+* How we are adding first-class fixed-point types to the Amaranth language
+* Lessons learned from shipping hardware (and some tricks for passing CE/EMC)
+
+ As we walk through each theme, this talk will include some live demos on a small Eurorack system demonstrating each.",,
+,,Normal,Greyhound: A RISC-V SoC with tightly coupled eFPGA on IHP SG13G2,Leo Moser,,"Greyhound is part RISC-V SoC and part eFPGA. Greyhound's embedded FPGA can be used as a custom instruction extension, as a peripheral or as a completely standalone FPGA with 32 I/Os. Custom tiles were created to enable warmboot functionality and allow communication with the SoC. Thanks to FABulous, the user bitstream for the FPGA can be generated using the upstream yosys and nextpnr toolchain.
+ 
+Greyhound was designed with open source EDA tools and the IHP Open Source PDK.",,
+,,Normal,Unified and Open Evaluation of LLMs for RTL Generation,Dario Garcia Gasulla,,"At the Barcelona Supercomputing Center (BSC) we are actively pushing research on LLMs for chip design. Our early contributions include an integrated evaluation framework (TuRTLe) to assess RTL code quality under syntax, functionality, synthesizability and PPA performance. Commited to open science, this is done in integration with open tools (Icarus, Yosis, OpenROAD), and publicly released for others to use and extend. This talk will include insights on the latest model performance, evaluation challenges and future research lines of work, towards improving the use of LLMs for EDA.",,
+,,Normal,HAgent an open framework to build hardware agents,Jose Renau,,[HAgent](https://github.com/masc-ucsc/hagent) is an open-source Hardware Agent infrastructure that integrates LLMs with chip design tools through a compiler-inspired pipeline architecture. The framework enables AI-assisted hardware development across with hermetic passes that communicate via YAML interfaces for enhanced debuggability and reproducibility.,,
+,,Normal,Just how far can you go with FOSS?,Peter Birch,,"Based on experience of guiding engineering at a silicon startup using FOSS tools and a strategy of open sourcing where possible, this presentation will explore where that limit is today, lessons learnt from this strategy, and some tips for others considering such an approach.",,
+,,Normal,Constrainedrandom - a Python package that does what it says on the tin,William Keen,,"Constrainedrandom is a Python package for - you guessed it - creating and solving constrained randomization problems. It's faster than PyVSC. It achieves this by walking the through state space randomly, rather than using exhaustive solutions for constraints. That makes it much faster for the majority case, though it's possible for it not to converge for harder problems.",,
+,,Normal,Transactron - hardware transactions for Amaranth HDL,Aria Węgrzyn,,"Overview of our open-source Transactron library https://github.com/kuznia-rdzeni/ for Amaranth HDL language, how it makes designing complex hardware easier, modular, solid and fun, introduction to the concept and demos.",,
+,,Normal,LibreLane: Looking to the future,Mohamed (Donn) Gaber,,"Designed to overcome the limitations of OpenLane but maintain its signature ease-of-configuration and ease-of-installation, LibreLane is the modular and extensible community-driven successor to the world’s most popular open source EDA flow, reimagining it as not just a flow, but as a customizable ASIC data flow infrastructure. In this talk, we will outline what motivated us to make LibreLane, what it’s currently capable of, and our future development plans, as well as a showcase of both simple and advanced use-cases it enables.",,
+,,Normal,Wildcat: Educational RISC-V Microprocessors,Martin Schoeberl,,"In computer architecture courses, we usually teach RISC processors using a five-stage pipeline, neglecting alternative organizations. This design choice, rooted in 1980s technology, may not be optimal today, and it is certainly not the easiest pipeline for education. This talk examines more straightforward pipeline organizations for RISC processors suitable for educational purposes and for implementing embedded processors in FPGAs and ASICs. We analyze resource costs and maximum clock frequency of various designs implemented in an FPGA, using clock frequency as a performance proxy. Additionally, we validate these results with ASIC designs synthesized using the open-source SkyWater130 process.
+ 
+Contradictory to common wisdom, a longer pipeline (up to 5 stages) does not necessarily always increase the maximum clock frequency. In two FPGA and one ASIC implementation, we discovered that a four- or five-stage pipeline leads to a slower clock frequency than a three-stage implementation. The reason is that the width of the forwarding multiplexer in the execution stage increases with longer pipelines, which is on the critical path. We also argue that a 3-stage pipeline organization is more adequate for teaching a pipeline organization of a microprocessor.",,
+,,Normal,SpiceBind: Integrating SPICE-Level Analog Models into RTL verification,Tomasz Hemperek,,"Open-source digital verification has advanced rapidly, but mixed-signal designs still lack a seamless path into modern RTL testbenches. This talk surveys today's community-driven options, pinpointing their remaining pain points.
+
+I then introduce [SpiceBind](https://github.com/themperek/spicebind), a lightweight VPI bridge that embeds an ngspice solver inside any VPI-capable simulator. RTL and SPICE devices step on the same timestep, while your existing testbench, coverage, and waveform tools remain unchanged.
+
+A top-level case study demonstrates how SpiceBind drops into a typical RTL simulation, and runs unmodified in a CI workflow. 
+
+Attendees will leave with an entirely open-source, reproducible recipe for bringing mixed-signal verification into their designed.",,
+,,Normal,Open-Source FPGA Test Visualization for cocotb,Grant Bowers,,"Junit outputs from cocotb are a useful building block for maintaining Continuous Integration (CI) for silicon projects. This can be extended through the use of OpenMetrics and Grafana to provide dashboards to present useful metrics and insights such as test coverage over time, simulator usage or bug tracking.",,
+,,Normal,10 Years of Chisel,Jack Koenig,,,,
+,,Normal,yosys-slang: SystemVerilog synthesis,Martin Povišer,,"""yosys-slang"" is a free and open extension for Yosys adding support for SystemVerilog design input. It has been used in two tapeouts and is seeing growing adoption in the community. The talk will cover the tool's status, future plans, and opportunities for other tools to build on top of its codebase.",,
+,,Normal,RV32I softcore and implementation from schematic to structural verilog (logilib) with verilator.,Jeremy Alcim,,RV32I softcore and implementation from schematic to structural verilog (logilib) with verilator.,,