+ ![]()
+
+
+ {{ headline }}
+
+ {{ subheading }}
+
+
+
+
+ 
+
+
+
+We are proud to finally release **LibreLane 3.0**.
+
+This release has been in development for quite some time and is packed with features.
+In addition to distributing LibreLane via Docker and Nix, we now also offer a LibreLane AppImage.
+
+The most noteworthy features are:
+
+- Support for the [ihp-sg13](https://github.com/IHP-GmbH/IHP-Open-PDK) PDK family.
+- A new "Chip" flow for pad ring generation.
+- New steps: "KLayout.Filler", "KLayout.SealRing", "KLayout.Density", and more.
+- SystemVerilog support through [yosys-slang](https://github.com/povik/yosys-slang).
+- Automatic clock gating through Yosys.
+- Much better antenna violation repair.
+- Many of the tools were updated.
+- Better coverage in our CI.
+
+But there are many small improvements as well, such as improved rendering of the chip layout, support for non-default rules, reduced file size of both magic and KLayout GDS, better subprocess formatting, and many more improvements and bug fixes.
+
+See the full release notes here: TODO
+
+
+
+::ff-btn-cta{linkTo="https://librelane.readthedocs.io/en/latest/" class="my-20"}
+Install LibreLane today.
+::
diff --git a/content/librelane/blog/index.md b/content/librelane/blog/index.md
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+---
+title: News
+layout: default
+header: News from LibreLane
+---
+
+::ff-libre-lane-news-overview
+::
diff --git a/content/librelane/index.md b/content/librelane/index.md
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+---
+title: "LibreLane - ASIC flow library"
+layout: default
+header: |
+ Free and open source silicon lives from its contributors.
+ And you can be one, too!
+ Read on for ways to get involved.
+---
+
+::ff-header-libre-lane
+::
+
+::ff-content-long
+LibreLane is a powerful and versatile infrastructure library that enables the construction of digital ASIC implementation flows based on open-source and commercial EDA tools. It includes a reference flow (Classic) that is built entirely using open-source EDA tools, and allowing designers to abstract the underlying tools and configure their behavior with a single configuration file.
+
+The key benefits of using LibreLane are:
+
+- Flexibility and extensibility: LibreLane is designed to be flexible and extensible, allowing designers to customize flows to meet their specific needs. This can be done by writing Python scripts and utilities, or by modifying the existing configuration file.
+
+- Open source: LibreLane is an open-source project, which means that it is freely available to use and modify. This makes it a good choice for designers who are looking for a cost-effective and transparent solution.
+
+- Community support: LibreLane capitalizes on LibreLane’s existing community of users and contributors. This means that there is a wealth of resources available to help designers get started and troubleshoot any problems they encounter.
+
+You can try LibreLane right in your browser:
+
+::center
+
+ ::ff-btn-cta{linkTo="https://colab.research.google.com/github/librelane/librelane/blob/main/notebook.ipynb" class="my-20"}
+ Try LibreLane in your Browser
+ ::
+
+
+
+ ::ff-btn-cta{linkTo="https://github.com/librelane" class="my-20"}
+ LibreLane Repository
+ ::
+
+
+
+ ::ff-btn-cta{linkTo="https://librelane.readthedocs.io/en/latest/" class="my-20"}
+ LibreLane Documentation
+ ::
+::
+::
+
+::ff-libre-lane-news
+::
+
+
+
+::center
+